公开(公告)号：US20140340133A1

公开(公告)日：2014-11-20

申请号：US14276567

申请日：2014-05-13

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics Pvt. Ltd.

Inventor： Gilles Gasiot ,  Sylvain Clerc ,  Junaid Yousuf ,  Maximilien Glorieux

IPC: H03K19/003 ,  H03L7/08

CPC classification number: H03K19/0033 ,  G11C5/005 ,  H03K3/0375 ,  H03K3/356121 ,  H03L7/08 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/095 ,  H03L7/18

Abstract: A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.

Abstract translation: 一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化 耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。

公开(公告)号：US20170227602A1

公开(公告)日：2017-08-10

申请号：US15244586

申请日：2016-08-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc ,  Gilles Gasiot

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318392 ,  G01R31/318566

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

公开(公告)号：US09000840B2

公开(公告)日：2015-04-07

申请号：US14134167

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Yvain Thonnart ,  Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel

IPC: H01L25/00 ,  H03K3/012 ,  G05F3/02 ,  H01L27/12 ,  H01L21/84 ,  H01L27/02 ,  H01L27/118 ,  H01L29/786

CPC classification number: H03K3/012 ,  G05F3/02 ,  G06F1/10 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648

Abstract: An integrated with a block including first and second oppositely doped semiconductor wells. There are standard cells placed next to one another, each standard cell including first transistors and a clock tree cell encircled by standard cells. The clock tree cell has a third semiconductor well with the same doping type as the doping of the first well and second transistors. The clock tree cell also has a semiconductor strip extending continuously around the third well and having the opposite doping type to the doping of the third well to electrically isolate the third well from the first well.

Abstract translation: 与包括第一和第二相对掺杂的半导体阱的块集成。 存在彼此相邻放置的标准单元，每个标准单元包括第一晶体管和由标准单元包围的时钟树单元。 时钟树单元具有与第一阱和第二晶体管的掺杂相同的掺杂类型的第三半导体阱。 时钟树单元还具有围绕第三阱连续延伸的半导体条，并且具有与第三阱的掺杂相反的掺杂类型，以将第三阱与第一阱电隔离。

公开(公告)号：US20180321308A1

公开(公告)日：2018-11-08

申请号：US16031395

申请日：2018-07-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc ,  Gilles Gasiot

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318392 ,  G01R31/318566

Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison.

公开(公告)号：US08937505B2

公开(公告)日：2015-01-20

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: H03K3/01 ,  G05F3/02 ,  H01L21/84 ,  H01L27/118 ,  H01L27/12 ,  H03K19/177 ,  H01L29/786

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US20140176228A1

公开(公告)日：2014-06-26

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US09748955B1

公开(公告)日：2017-08-29

申请号：US15363041

申请日：2016-11-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Gilles Gasiot ,  Victor Malherbe ,  Sylvain Clerc

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/21 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H03K19/00338 ,  H01L21/823892 ,  H01L27/0266 ,  H01L27/092 ,  H01L27/0928 ,  H03K19/21

Abstract: A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.

公开(公告)号：US09634671B2

公开(公告)日：2017-04-25

申请号：US14734316

申请日：2015-06-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Martin Cochet ,  Sylvain Clerc

IPC: G06F1/04 ,  H03K21/38 ,  G06F1/08 ,  H03L7/081 ,  H03K23/64

CPC classification number: H03K21/38 ,  G06F1/08 ,  H03K23/64 ,  H03L7/081

Abstract: A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.

公开(公告)号：US20160079984A1

公开(公告)日：2016-03-17

申请号：US14734316

申请日：2015-06-09

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Martin Cochet ,  Sylvain Clerc

IPC: H03K21/38

CPC classification number: H03K21/38 ,  G06F1/08 ,  H03K23/64 ,  H03L7/081

Abstract: A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal.

Abstract translation: 脉冲信号发生器具有接收具有初始周期的初始脉冲信号的输入，产生振荡器信号的振荡器，第一级和第二级。 第一级与振荡器信号同步，并被配置为传送具有表示初始周期的除法的整数部分整数N的连续脉冲之间的间隔的次级脉冲信号。第一级还传送辅助信号 代表除法的分数部分，并且对于次级脉冲信号的每个脉冲包含考虑到分离而应用于脉冲的时间偏移的指示。 第二级被配置为接收连续脉冲和对应的时移指示，并产生输出脉冲信号的连续对应的脉冲。

公开(公告)号：US08837206B2

公开(公告)日：2014-09-16

申请号：US13669226

申请日：2012-11-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Maximilien Glorieux ,  Sylvain Clerc ,  Gilles Gasiot ,  Phillippe Roche

IPC: G11C11/00

CPC classification number: G11C19/28

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract translation: 存储器装置包括交叉耦合在第一和第二节点之间的第一和第二反相器。 第一反相器被配置为经由第一晶体管由第一电源电压提供，并且第二反相器被配置为经由第二晶体管由第一电源电压提供。 第一控制电路被配置为基于第二节点处的电压和第二晶体管的栅极节点来控制第一晶体管的栅极节点。 第二控制电路被配置为基于第一晶体管的第一节点处和栅极节点处的电压来控制第二晶体管的栅极节点。