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公开(公告)号：US12086008B2
公开(公告)日：2024-09-10
申请号：US17942354
申请日：2022-09-12
发明人： Jerome Lacan , Remi Collette , Christophe Eva , Milan Komarek
IPC分类号： G06F1/3225 , G06F1/3287 , H03K19/017
CPC分类号： G06F1/3225 , G06F1/3287 , H03K19/01742
摘要： A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.
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2.发明授权公开(公告)号：US11245405B2
公开(公告)日：2022-02-08
申请号：US17352849
申请日：2021-06-21
摘要： A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.
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公开(公告)号：US20200174927A1
公开(公告)日：2020-06-04
申请号：US16669184
申请日：2019-10-30
摘要： A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.
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公开(公告)号：US11189360B2
公开(公告)日：2021-11-30
申请号：US16669184
申请日：2019-10-30
摘要： A system includes a memory device that includes a first memory region to store first data at first addresses, and a second memory region to store, on command, either second data at second addresses or error correction code check bits associated with the first data at third addresses.
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公开(公告)号：US11120887B2
公开(公告)日：2021-09-14
申请号：US17096090
申请日：2020-11-12
摘要： An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.
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6.发明授权公开(公告)号：US11115038B2
公开(公告)日：2021-09-07
申请号：US16923335
申请日：2020-07-08
摘要： The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
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公开(公告)号：US20210158887A1
公开(公告)日：2021-05-27
申请号：US17096090
申请日：2020-11-12
摘要： An embodiment method for writing to a volatile memory comprises at least receiving a request to write to the memory, and, in response to each request to write to the memory: preparation of data to be written to the memory, this comprising computing an error correction code; storing in a buffer register the data to be written to the memory; and, if no new request to write to or to read from the memory is received after the storage, writing to the memory of the data to be written stored in the buffer register.
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公开(公告)号：US11495275B2
公开(公告)日：2022-11-08
申请号：US17336841
申请日：2021-06-02
摘要： A random access memory is connected to a processing unit through a memory interface. Access to the random access is memory is controlled by a process. The memory interface receives a request for access to the memory issued by the processing unit. In response to the request, the memory interface indicates to the processing unit that the memory is not available to receive another access request during a duration of unavailability. This duration can be differentiated depending on whether the received request is a write or read request. The value of the duration of unavailability associated with a write request and the value of the duration of unavailability associated with a read request are individually programmable independently of each other.
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