公开(公告)号：US20220300389A1

公开(公告)日：2022-09-22

申请号：US17208935

申请日：2021-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Balwinder Singh Soni ,  Amritanshu Anand ,  Venkata Narayanan Srinivasan

IPC: G06F11/27 ,  G01R31/3177 ,  G06F1/08

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.

公开(公告)号：US12118376B2

公开(公告)日：2024-10-15

申请号：US17235206

申请日：2021-04-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GmbH

Inventor： Deepak Baranwal ,  Amritanshu Anand ,  Roberto Colombo ,  Boris Vittorelli

IPC: G06F9/455 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/455 ,  G06F9/45533 ,  G06F9/48 ,  G06F9/4812 ,  G06F9/4843 ,  G06F9/485 ,  G06F9/4856 ,  G06F9/4881 ,  G06F9/50 ,  G06F9/5083 ,  G06F9/5088 ,  G06F2009/4557 ,  G06F2009/45575

Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.

公开(公告)号：US11835991B2

公开(公告)日：2023-12-05

申请号：US17208935

申请日：2021-03-22

Applicant: STMicroelectronics International N.V.

Inventor： Amulya Pandey ,  Balwinder Singh Soni ,  Amritanshu Anand ,  Venkata Narayanan Srinivasan

IPC: G06F11/27 ,  G01R31/3177 ,  G06F1/08

CPC classification number: G06F11/27 ,  G01R31/3177 ,  G06F1/08

Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.