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公开(公告)号：US20200007129A1
公开(公告)日：2020-01-02
申请号：US16452051
申请日：2019-06-25
Inventor： Andrea Mario Veggetti , Abhishek Jain
IPC: H03K19/003 , H03K3/037 , H03K3/356 , G01R31/3181 , G11C7/10
Abstract: A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.
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2.发明授权公开(公告)号：US09543044B2
公开(公告)日：2017-01-10
申请号：US14074341
申请日：2013-11-07
Inventor： Abhishek Jain , Andrea Mario Veggetti , Amit Chhabra
Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。
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3.发明申请公开(公告)号：US20150127998A1
公开(公告)日：2015-05-07
申请号：US14074341
申请日：2013-11-07
Applicant: STMicroelectronics International N.V.
Inventor： Andrea Mario Veggetti , Abhishek Jain , Amit Chhabra
Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.
Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。
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