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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US20210366554A1
公开(公告)日：2021-11-25
申请号：US17306266
申请日：2021-05-03
Inventor： Fabio Enrico Carlo Disegni , Laura Capecchi , Marcella Carissimi , Vikas Rana , Cesare Torti
Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US20250069656A1
公开(公告)日：2025-02-27
申请号：US18813662
申请日：2024-08-23
Applicant: STMicroelectronics International N.V.
Inventor： Maurizio Francesco Perroni , Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré , Massimo Caruso
IPC: G11C13/00
Abstract: A memory device comprises a memory array having memory cells in a set of memory portions and addressable via a pair of row and column values, a set of sense amplifier circuits coupled to and interposed between adjacent memory portions, a control logic circuit configured to provide at least one address signal indicating a pair of row and column values to localize at least one addressed memory cell, and to issue read or write access requests towards the at least one addressed memory cell, a first set of access devices configured to couple an addressed memory cell in a respective memory portion to a respective sense amplifier circuit in response to a read access request, and a second set of access devices configured to couple an addressed memory cell in a respective memory portion to a main programming bitline in response to a write access request.
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公开(公告)号：US20250030418A1
公开(公告)日：2025-01-23
申请号：US18764672
申请日：2024-07-05
Applicant: STMicroelectronics International N.V.
Inventor： Maurizio Francesco Perroni , Davide Manfré , Massimo Caruso , Cesare Torti , Fabio Enrico Carlo Disegni
IPC: H03K17/687
Abstract: A switch circuit includes a first and a second input nodes to receive a first and a second input voltages, and an output node to produce an output voltage switchable between the first and second input voltages. A first and a second pass devices are arranged in series between the first input node and the output node. A third and a fourth pass devices are arranged in series between the second input node and the output node. A first, a second, a third, and a fourth elevator circuits control, respectively, the first, second, third, and fourth pass devices. The first elevator circuit is biased between the first input voltage and a shifted ground voltage. The third elevator circuit is biased between the second input voltage and a ground voltage. The second and fourth elevator circuits are biased between the output voltage and an elevated ground voltage.
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公开(公告)号：US20250078926A1
公开(公告)日：2025-03-06
申请号：US18817969
申请日：2024-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Davide Manfré , Maurizio Francesco Perroni , Massimo Caruso , Fabio Enrico Carlo Disegni , Cesare Torti
IPC: G11C13/00
Abstract: A non-volatile memory includes a row decoder comprising, for each word-line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word-lines to ground. The row decoder comprises a demultiplexer connected to a second supply voltage smaller than the first, and configured to assert an enable signal as a function of an address signal. The switching circuit comprises two n-channel FETs connected in series between the word-line and ground, with the gate terminal of one FET connected to a first signal and the gate terminal of the other FET connected to a second voltage. A bias circuit is configured to set the voltage between the two FETs to the second voltage when the FETs are opened. The switching circuit comprises a p-channel FET connected between the word-line and the second voltage, and a gate terminal connected to a second signal.
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Patent Agency Ranking
公开(公告)号：US11380393B2
公开(公告)日：2022-07-05
申请号：US17129016
申请日：2020-12-21
Applicant: STMicroelectronics International N.V.
Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.
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公开(公告)号：US20210193221A1
公开(公告)日：2021-06-24
申请号：US17129016
申请日：2020-12-21
Applicant: StMicroelectronics International N.V.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.
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公开(公告)号：US11355191B2
公开(公告)日：2022-06-07
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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9.发明申请公开(公告)号：US20190214079A1
公开(公告)日：2019-07-11
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
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公开(公告)号：US20190043574A1
公开(公告)日：2019-02-07
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
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