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公开(公告)号：US11475960B2
公开(公告)日：2022-10-18
申请号：US17306266
申请日：2021-05-03
IPC分类号： G11C13/00 , G11C16/10 , G11C7/06 , G11C16/08 , G11C16/24 , G11C16/28 , G11C16/30 , G11C16/32
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US09990245B2
公开(公告)日：2018-06-05
申请号：US14951639
申请日：2015-11-25
IPC分类号： G06F11/00 , G06F11/07 , G06F11/08 , G06F11/16 , G11C29/42 , G11C29/02 , G11B20/18 , G06F11/10 , G11C29/04
CPC分类号： G06F11/079 , G06F11/073 , G06F11/0751 , G06F11/076 , G06F11/0772 , G06F11/08 , G06F11/1004 , G06F11/16 , G11B2020/1843 , G11C29/02 , G11C29/04 , G11C29/42
摘要： An electronic device includes a memory having memory locations being subject to transient faults and permanent faults, and a fault detection circuit coupled to the memory. The fault detection circuit is configured to read the memory locations at a first time, and determine a first fault count and fault map signature including the transient and permanent faults at the first time based upon reading the plurality of memory locations, and to store the first fault count and fault map signature. The fault detection circuit is configured to read the memory locations at a second time and determine a second fault count and fault map signature including the transient and permanent faults at the second time based upon reading the memory locations, and compare the stored first fault count and fault map signature with the second fault count and fault map signature to determine a permanent fault count.
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公开(公告)号：US20210366554A1
公开(公告)日：2021-11-25
申请号：US17306266
申请日：2021-05-03
摘要： An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.
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公开(公告)号：US11380393B2
公开(公告)日：2022-07-05
申请号：US17129016
申请日：2020-12-21
摘要： An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.
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公开(公告)号：US20210193221A1
公开(公告)日：2021-06-24
申请号：US17129016
申请日：2020-12-21
IPC分类号： G11C13/00
摘要： An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.
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6.发明授权公开(公告)号：US11256442B2
公开(公告)日：2022-02-22
申请号：US17087070
申请日：2020-11-02
IPC分类号： G06F3/06
摘要： A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.
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公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
IPC分类号： G11C13/00
摘要： An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
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公开(公告)号：US20210125668A1
公开(公告)日：2021-04-29
申请号：US17072887
申请日：2020-10-16
IPC分类号： G11C13/00
摘要： An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
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公开(公告)号：US10901919B2
公开(公告)日：2021-01-26
申请号：US16455155
申请日：2019-06-27
摘要： A circuit, for managing operations for accessing a flash memory on the basis of requests received from a main CPU and from an auxiliary CPU, may be configured to: associate with the main CPU, a higher access priority to the flash memory than the access priority of the auxiliary CPU; command, in the absence of further requests for accessing the flash memory, the access to the flash memory for the main or auxiliary CPU which has initiated a first access request; verify, following a receipt of a second access request, the access priority associated with this second access request; suspend one of the first or the second access request having lower priority; and authorize the other of the first or the second access request having higher priority.
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10.发明授权公开(公告)号：US10824417B2
公开(公告)日：2020-11-03
申请号：US16225557
申请日：2018-12-19
IPC分类号： G06F8/654 , G11C7/22 , G06F8/656 , G06F8/658 , G11C13/00 , H04L29/08 , G11C11/22 , G11C11/16
摘要： A method for management of a differential memory includes storing first logic data associated with a first informative content in an auxiliary memory module of the differential memory; storing third logic data associated with a second informative content in a second submodule of a main memory module by overwriting second logic data associated with the first informative content while maintaining the first logic data contained in a first submodule of the main memory module unaltered; when the third logic data is being stored, reading the first logic data from the auxiliary memory module in a single-ended mode in response to a request for reading the first informative content; otherwise, reading the first logic data from the first submodule; and reading the third logic data in single-ended mode.
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