公开(公告)号：US20240364347A1

公开(公告)日：2024-10-31

申请号：US18623331

申请日：2024-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Rupesh SINGH ,  Ankur BAL ,  Kirtiman Singh RATHORE

IPC: H03L7/00 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/20

CPC classification number: H03L7/00 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/20

Abstract: A first latching circuit has a reset function controlled by a reset signal and configured to latch a logic state in response to a first edge of a clock signal to generate a first output signal. A second latching circuit has a reset function controlled by that reset signal and configured to latch a logic state in response to a second edge of that clock signal to generate a second output signal. The first and second edges are opposite edges. A combinatorial logic circuit logically combines the first and second output signals to generate a logic output signal. A third latching circuit has a reset function controlled by that reset signal and configured to latch the logic output signal in response to the second edge of that clock signal to generate a reset synchronization control signal.

公开(公告)号：US20240113741A1

公开(公告)日：2024-04-04

申请号：US18471162

申请日：2023-09-20

Applicant: STMicroelectronics International N.V.

Inventor： Sameer VASHISHTHA ,  Kirtiman Singh RATHORE ,  Paras GARG

IPC: H04B1/44 ,  H03K19/00 ,  H04B17/11

CPC classification number: H04B1/44 ,  H03K19/0005 ,  H04B17/11

Abstract: An integrated circuit includes a current mode transmitter. The current mode transmitter includes a first resistor and a second resistor. The resistance of the first resistor is adjusted by measuring the resistance, generating a resistance trimming code based on the measured resistance, and writing the first resistance trimming code to a first register. The resistance of the second resistor is adjusted by generating a second resistance trimming code based on the first resistance trimming code and writing the second resistance trimming code to a second register.