公开(公告)号：US20240113741A1

公开(公告)日：2024-04-04

申请号：US18471162

申请日：2023-09-20

Applicant: STMicroelectronics International N.V.

Inventor： Sameer VASHISHTHA ,  Kirtiman Singh RATHORE ,  Paras GARG

IPC: H04B1/44 ,  H03K19/00 ,  H04B17/11

CPC classification number: H04B1/44 ,  H03K19/0005 ,  H04B17/11

Abstract: An integrated circuit includes a current mode transmitter. The current mode transmitter includes a first resistor and a second resistor. The resistance of the first resistor is adjusted by measuring the resistance, generating a resistance trimming code based on the measured resistance, and writing the first resistance trimming code to a first register. The resistance of the second resistor is adjusted by generating a second resistance trimming code based on the first resistance trimming code and writing the second resistance trimming code to a second register.

公开(公告)号：US20210067159A1

公开(公告)日：2021-03-04

申请号：US16999813

申请日：2020-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Paras GARG ,  Ankit AGRAWAL ,  Sandeep KAUSHIK

IPC: H03K17/687 ,  H03K19/0185

Abstract: In various embodiments, the present disclosure provides low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods. In one embodiment, a LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

公开(公告)号：US20200014387A1

公开(公告)日：2020-01-09

申请号：US16503960

申请日：2019-07-05

Applicant: STMicroelectronics International N.V.

Inventor： Atul DWIVEDI ,  Paras GARG ,  Kallol CHATTERJEE

IPC: H03K19/0185 ,  G01R31/317

Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

公开(公告)号：US20240128971A1

公开(公告)日：2024-04-18

申请号：US18481907

申请日：2023-10-05

Applicant: STMicroelectronics International N.V.

Inventor： Sameer VASHISHTHA ,  Saiyid Mohammad Irshad RIZVI ,  Paras GARG

IPC: H03K17/56

CPC classification number: H03K17/56 ,  H03K2005/00078

Abstract: An integrated circuit includes a current mode transmitter having a first driver and a second driver. The first driver receives a single bit data stream. The second driver receives a delayed data stream corresponding to the single bit data stream delayed by a clock cycle. The current mode transmitter has a transition detector that generates a bulk modulation signal having a first value when the single bit data stream is the same as the delayed data stream and having a second value when the single bit data stream is different from the delayed data stream. The transition detector supplies the bulk modulation signal to the bulk terminals of driver switches of the first and second drivers.

公开(公告)号：US20240039537A1

公开(公告)日：2024-02-01

申请号：US18356146

申请日：2023-07-20

Applicant: STMicroelectronics International N.V.

Inventor： Manoj KUMAR ,  Paras GARG ,  Saiyid Mohammad Irshad RIZVI

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: The present disclosure is directed to a high-voltage fault protection for an interface circuit. The interface circuit is transmitting data signals through an output driver to an external circuit coupled to a PAD contact. The output driver includes pull-up and pull-down drivers. The pull-up driver includes two series PMOS coupled between a voltage supply and the PAD. The pull-down driver includes two series NMOS coupled between the PAD and a ground node. A first safe signal is coupled to one PMOS. A first circuit scheme is designed to generate the first safe signal to be low-logical level voltage when the PAD voltage is lower than a threshold, while being high-logical level voltage when the PAD voltage is higher than the threshold. A second circuit scheme is designed to control one of the series NMOS to be in OFF state when the PAD voltage is higher than the threshold.

公开(公告)号：US20230275586A1

公开(公告)日：2023-08-31

申请号：US18098421

申请日：2023-01-18

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep KAUSHIK ,  Paras GARG

IPC: H03K19/0185 ,  H03K17/687 ,  H03K19/017

CPC classification number: H03K19/018514 ,  H03K19/018585 ,  H03K17/6871 ,  H03K19/01707

Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.