公开(公告)号：US09264045B2

公开(公告)日：2016-02-16

申请号：US14231939

申请日：2014-04-01

Applicant: STMicroelectronics International N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K5/08 ,  H03K19/0948 ,  H03K19/003 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。

公开(公告)号：US09843321B2

公开(公告)日：2017-12-12

申请号：US15265627

申请日：2016-09-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sameer Vashishtha

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  H03K19/0185 ,  H03K5/12

CPC classification number: H03K17/687 ,  H03K5/12 ,  H03K19/0185 ,  H03K19/018507

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

公开(公告)号：US20170005655A1

公开(公告)日：2017-01-05

申请号：US15265627

申请日：2016-09-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sameer Vashishtha

IPC: H03K17/687 ,  H03K5/12 ,  H03K19/0185

CPC classification number: H03K17/687 ,  H03K5/12 ,  H03K19/0185 ,  H03K19/018507

Abstract: A drive circuit includes an input, a driver, a first buffer, a second buffer, a first capacitance element, and a second capacitance element. The driver includes a first PMOS transistor and a first NMOS transistor coupled in series between a supply terminal and a reference terminal. The first buffer is coupled between the input and a control terminal of the first PMOS transistor. The second buffer is coupled between the input and a control terminal of the first NMOS transistor. The first capacitance element is coupled to the control terminal of the first PMOS transistor through a first semiconductor switch. The second capacitance element is coupled to the control terminal of the first NMOS transistor through a second semiconductor switch.

Abstract translation: 驱动电路包括输入，驱动器，第一缓冲器，第二缓冲器，第一电容元件和第二电容元件。 驱动器包括串联耦合在电源端子和参考端子之间的第一PMOS晶体管和第一NMOS晶体管。 第一缓冲器耦合在第一PMOS晶体管的输入端和控制端之间。 第二缓冲器耦合在第一NMOS晶体管的输入端和控制端之间。 第一电容元件通过第一半导体开关耦合到第一PMOS晶体管的控制端。 第二电容元件通过第二半导体开关耦合到第一NMOS晶体管的控制端子。

公开(公告)号：US20150280716A1

公开(公告)日：2015-10-01

申请号：US14231939

申请日：2014-04-01

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Sameer Vashishtha ,  Saiyid Mohammad Irshad Rizvi

IPC: H03K19/0948 ,  H03K19/0185 ,  H03K19/00 ,  H03K19/003

CPC classification number: H03K19/09487 ,  H03K19/0027 ,  H03K19/00361 ,  H03K19/018521

Abstract: A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.

Abstract translation: 缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。 第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。 第二反相器与第一反相器的输出串联。 第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是 大于第一高电压。 反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。