公开(公告)号：US20210067144A1

公开(公告)日：2021-03-04

申请号：US17005091

申请日：2020-08-27

Applicant: STMicroelectronics International N.V.

Inventor： Manish GARG ,  Ankit AGRAWAL

IPC: H03K3/0233 ,  H03K3/037

Abstract: A delay independent differential hysteresis receiver. The differential hysteresis receiver uses two parallel paths in a first receiver stage, each path having a comparator with a dedicated offset on the complimentary inputs. A second receiver stage includes a hold circuit that brings the two parallel paths of the first receiver stage together to form a receiver hysteresis output.

公开(公告)号：US20150263726A1

公开(公告)日：2015-09-17

申请号：US14216701

申请日：2014-03-17

Applicant: STMicroelectronics International N.V.

Inventor： Ankit AGRAWAL

IPC: H03K17/687 ,  H01L27/12 ,  H01L29/10 ,  H01L29/423 ,  H03K17/10 ,  H01L27/092

CPC classification number: H03K17/102 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/42364 ,  H01L29/7838 ,  H01L29/78648 ,  H03K17/6872

Abstract: An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Abstract translation: 逆变器在FDSOI集成电路管芯中实现。 反相器包括PMOS晶体管和NMOS晶体管。 PMOS和NMOS晶体管各自包括耦合到晶体管的相应源极端子的第一栅极。 PMOS和NMOS晶体管各自包括耦合到反相器的输入的背栅。

公开(公告)号：US20210067159A1

公开(公告)日：2021-03-04

申请号：US16999813

申请日：2020-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Paras GARG ,  Ankit AGRAWAL ,  Sandeep KAUSHIK

IPC: H03K17/687 ,  H03K19/0185

Abstract: In various embodiments, the present disclosure provides low-voltage differential signaling (LVDS) receiver circuits, electronic devices, and methods. In one embodiment, a LVDS receiver includes an input differential pair of transistors that receive a differential input signal. The input differential pair includes a first NMOS transistor that receives a first input signal and a second NMOS transistor that receives a second input signal. A third NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the first NMOS transistor, and a fourth NMOS transistor has source and drain terminals respectively coupled to source and drain terminals of the second NMOS transistor. A first level shifter is coupled to a gate of the third NMOS transistor, and a second level shifter is coupled to a gate of the fourth NMOS transistor.

公开(公告)号：US20160111534A1

公开(公告)日：2016-04-21

申请号：US14985264

申请日：2015-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anand KUMAR ,  Ankit AGRAWAL

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L29/51 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/7831 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/78648

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.