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公开(公告)号：US10224097B2
公开(公告)日：2019-03-05
申请号：US15909261
申请日：2018-03-01
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Kumar , Vinay Kumar , Kedar Janardan Dhori
IPC: G11C11/419 , G11C11/418 , G11C5/14 , G11C5/06
Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
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2.发明申请公开(公告)号：US20180190346A1
公开(公告)日：2018-07-05
申请号：US15909261
申请日：2018-03-01
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Kumar , Vinay Kumar , Kedar Janardan Dhori
IPC: G11C11/419 , G11C5/14 , G11C11/418
CPC classification number: G11C11/419 , G11C5/063 , G11C5/145 , G11C5/147 , G11C11/418
Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
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Patent Agency Ranking
公开(公告)号：US09208040B2
公开(公告)日：2015-12-08
申请号：US14266067
申请日：2014-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Harsh Rawat , Kedar Janardan Dhori , Vinay Kumar , PraveenKumar Verma
CPC classification number: G11C29/702 , G06F11/2094 , G06F2201/85
Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.
Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。
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公开(公告)号：US20150317225A1
公开(公告)日：2015-11-05
申请号：US14266067
申请日：2014-04-30
Applicant: STMicroelectronics International N.V.
Inventor： Harsh Rawat , Kedar Janardan Dhori , Vinay Kumar , PraveenKumar Verma
IPC: G06F11/20
CPC classification number: G11C29/702 , G06F11/2094 , G06F2201/85
Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.
Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。
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公开(公告)号：US09685209B1
公开(公告)日：2017-06-20
申请号：US15132388
申请日：2016-04-19
Applicant: STMicroelectronics International N.V.
Inventor： Kedar Janardan Dhori , Vinay Kumar , Ashish Kumar
Abstract: A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.
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公开(公告)号：US09940997B2
公开(公告)日：2018-04-10
申请号：US15447853
申请日：2017-03-02
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Kumar , Vinay Kumar , Kedar Janardan Dhori
IPC: G11C11/00 , G11C11/419 , G11C11/418 , G11C5/14
CPC classification number: G11C11/419 , G11C5/063 , G11C5/145 , G11C5/147 , G11C11/418
Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
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公开(公告)号：US20170316820A1
公开(公告)日：2017-11-02
申请号：US15447853
申请日：2017-03-02
Applicant: STMicroelectronics International N.V.
Inventor： Ashish Kumar , Vinay Kumar , Dhori Kedar Janardan
IPC: G11C11/419 , G11C11/418
CPC classification number: G11C11/419 , G11C5/063 , G11C5/145 , G11C5/147 , G11C11/418
Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
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