公开(公告)号：US20240345987A1

公开(公告)日：2024-10-17

申请号：US18756821

申请日：2024-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

公开(公告)号：US11942961B2

公开(公告)日：2024-03-26

申请号：US17713033

申请日：2022-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Oreggia ,  Marco Cignoli

IPC: H03M1/10 ,  H03M1/56 ,  H03M1/66 ,  H03M1/68

CPC classification number: H03M1/1071 ,  H03M1/56 ,  H03M1/662 ,  H03M1/687

Abstract: An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

公开(公告)号：US12056080B2

公开(公告)日：2024-08-06

申请号：US17732114

申请日：2022-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.