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    HIGH SPEED DATA TRANSMISSION IN BATTERY MANAGEMENT SYSTEMS WITH ISOLATED SPI INTERFACE
    1.
    发明公开
    HIGH SPEED DATA TRANSMISSION IN BATTERY MANAGEMENT SYSTEMS WITH ISOLATED SPI INTERFACE 审中-公开

    公开(公告)号：US20240345987A1

    公开(公告)日：2024-10-17

    申请号：US18756821

    申请日：2024-06-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

    IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

    Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

    Circuit arrangement for validation of operation of a logic module in a multipower logic architecture and corresponding validation method
    3.
    发明授权
    Circuit arrangement for validation of operation of a logic module in a multipower logic architecture and corresponding validation method 有权

    公开(公告)号：US12174252B2

    公开(公告)日：2024-12-24

    申请号：US18324583

    申请日：2023-05-26

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Diego Alagna ,  Alessandro Cannone

    IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/08

    Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

    High speed data transmission in battery management systems with isolated SPI interface
    5.
    发明授权
    High speed data transmission in battery management systems with isolated SPI interface 有权

    公开(公告)号：US12056080B2

    公开(公告)日：2024-08-06

    申请号：US17732114

    申请日：2022-04-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

    IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

    CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

    Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

    Circuit for driving an inductive load, corresponding device, vehicle and method
    7.
    发明授权
    Circuit for driving an inductive load, corresponding device, vehicle and method 有权

    公开(公告)号：US11789048B2

    公开(公告)日：2023-10-17

    申请号：US17340559

    申请日：2021-06-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vanni Poletto ,  Nicola Errico ,  Paolo Vilmercati ,  Marco Cignoli ,  Vincenzo Salvatore Genna ,  Diego Alagna

    IPC: G01R19/165 ,  H01H47/02 ,  H01H47/32

    CPC classification number: G01R19/1659 ,  H01H47/02 ,  H01H47/325

    Abstract: An embodiment circuit comprises high-side and low-side switches arranged between supply and reference nodes, and having an intermediate node. A switching control signal is applied with opposite polarities to the high-side and low-side switches. An inductive load is coupled between the intermediate node and one of the supply and reference nodes. Current sensing circuitry is configured to sample a first value of the load current flowing in one of the high-side and low-side switches before a commutation of the switching control signal, sample a second value of the load current flowing in the other of the high-side and low-side switches after the commutation of the switching control signal, sample a third value of the load current flowing in the other of the high-side and low-side switches after the second sampling, and generate a failure signal as a function of the first, second and third sampled values of the load current.

    Communication method, corresponding system and device
    8.
    发明授权
    Communication method, corresponding system and device 有权

    公开(公告)号：US11575404B2

    公开(公告)日：2023-02-07

    申请号：US17480926

    申请日：2021-09-21

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Lucia Maggio ,  Marzia Annovazzi ,  Diego Alagna

    IPC: H04B1/44 ,  H04L25/02

    Abstract: A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.

    CIRCUIT FOR DRIVING AN INDUCTIVE LOAD, CORRESPONDING DEVICE, VEHICLE AND METHOD
    10.
    发明申请
    CIRCUIT FOR DRIVING AN INDUCTIVE LOAD, CORRESPONDING DEVICE, VEHICLE AND METHOD 有权

    公开(公告)号：US20210389351A1

    公开(公告)日：2021-12-16

    申请号：US17340559

    申请日：2021-06-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Vanni Poletto ,  Nicola Errico ,  Paolo Vilmercati ,  Marco Cignoli ,  Vincenzo Salvatore Genna ,  Diego Alagna

    IPC: G01R19/165 ,  H01H47/32 ,  H01H47/02

    Abstract: An embodiment circuit comprises high-side and low-side switches arranged between supply and reference nodes, and having an intermediate node. A switching control signal is applied with opposite polarities to the high-side and low-side switches. An inductive load is coupled between the intermediate node and one of the supply and reference nodes. Current sensing circuitry is configured to sample a first value of the load current flowing in one of the high-side and low-side switches before a commutation of the switching control signal, sample a second value of the load current flowing in the other of the high-side and low-side switches after the commutation of the switching control signal, sample a third value of the load current flowing in the other of the high-side and low-side switches after the second sampling, and generate a failure signal as a function of the first, second and third sampled values of the load current.

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