公开(公告)号：US20180240523A1

公开(公告)日：2018-08-23

申请号：US15692158

申请日：2017-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele MANGANO ,  Michele Alessandro CARRANO ,  Gaetano DI STEFANO ,  Roberto Sebastiano RUGGIRELLO

IPC: G11C16/10 ,  G11C8/20 ,  G11C13/00

CPC classification number: G11C16/10 ,  G06F12/0246 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/461 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7209 ,  G11C8/20 ,  G11C13/004 ,  G11C13/0069

Abstract: A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.

公开(公告)号：US20180260585A1

公开(公告)日：2018-09-13

申请号：US15916067

申请日：2018-03-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mirko DONDINI ,  Gaetano DI STEFANO ,  Sergio ABENDA ,  Layachi DAINECHE

IPC: G06F21/85 ,  G06F21/71 ,  G06F13/40

CPC classification number: G06F21/85 ,  G06F13/4068 ,  G06F21/606 ,  G06F21/71 ,  G06F21/76

Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.