公开(公告)号：US12188991B2

公开(公告)日：2025-01-07

申请号：US17678953

申请日：2022-02-23

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Gaudenzia Bagnati

IPC: G01R31/52 ,  H03K5/24 ,  H03K17/08

Abstract: A device includes a driver circuit and diagnostic circuitry coupled to the driver circuit. The diagnostic circuitry includes an on-state diagnostic circuit and an off-state diagnostic circuit. The diagnostic circuitry, in operation: generates a configuration signal associated with an operative condition of the driver circuit based on a comparator output of the off-state diagnostic circuit; diagnoses conditions associated with the driver circuit; and controls operation of the on-state diagnostic circuit based on the configuration signal.

公开(公告)号：US11885845B2

公开(公告)日：2024-01-30

申请号：US17678772

申请日：2022-02-23

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Gaudenzia Bagnati ,  Stefano Castorina ,  Valerio Bendotti

IPC: G01R31/02 ,  H03K17/687 ,  H03K5/24 ,  G01R31/54 ,  G01R19/165 ,  G01R31/28

CPC classification number: G01R31/2851 ,  G01R19/16571 ,  G01R31/54 ,  H03K5/24 ,  H03K17/6874 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: An integrated circuit includes a plurality of power transistor driver channels for driving external loads. The driver channels can be selectively configured as high-side (HS) or low-side (LS) driver channels. The integrated circuit includes, for each driver channel, a respective on-state test circuit and a respective controller. The on-state test circuits can be selectively configured to test for HS overcurrent conditions, LS overcurrent conditions, HS open load conditions, and LS open load conditions.

公开(公告)号：US11979143B2

公开(公告)日：2024-05-07

申请号：US17870173

申请日：2022-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Valerio Bendotti ,  Luca Finazzi ,  Gaudenzia Bagnati

IPC: H03K17/16 ,  H02M3/158

CPC classification number: H03K17/162 ,  H02M3/158 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.