公开(公告)号：US09520468B2

公开(公告)日：2016-12-13

申请号：US14166075

申请日：2014-01-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo Magri′ ,  Antonino Sebastiano Alessandria ,  Stefania Fortuna ,  Leonardo Fragapane

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power device integrated on a semiconductor substrate and having a plurality of conductive bridges within a trench gate structure. In an embodiment, a semiconductor substrate includes a trench having sidewalls and a bottom, the walls and bottom are covered with a first insulating coating layer which then also includes a conductive gate structure. An embodiment provides the formation of the conductive gate structure with covering at least the sidewalls with a second conductive coating layer of a first conductive material. This results in a conductive central region of a second conductive material having a different resistivity than the first conductive material forming a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 集成在半导体衬底上并在沟槽栅极结构内具有多个导电桥的功率器件。 在一个实施例中，半导体衬底包括具有侧壁和底部的沟槽，壁和底部被第一绝缘涂层覆盖，然后第一绝缘涂层还包括导电栅极结构。 一个实施例提供形成导电栅极结构，至少用第一导电材料的第二导电涂层覆盖侧壁。 这导致第二导电材料的导电中心区域具有与第一导电材料不同的电阻率，该第一导电材料在所述第二导电涂层和所述导电中心区域之间形成多个导电桥。

公开(公告)号：US11728422B2

公开(公告)日：2023-08-15

申请号：US17096697

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo Magri' ,  Stefania Fortuna

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L21/765 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734

Abstract: A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.

公开(公告)号：US09006063B2

公开(公告)日：2015-04-14

申请号：US13931637

申请日：2013-06-28

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte, Ltd.

Inventor： Yean Ching Yong ,  Stefania Fortuna

IPC: H01L21/8242 ,  H01L21/336 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/26513 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: A method for forming a trench MOSFET includes doping a body region of the trench MOSFET in multiple ion implantation steps each having different ion implantation energy. The method further comprises etching the trench to a depth of about 1.7 μm.

Abstract translation: 一种形成沟槽MOSFET的方法包括：在具有不同离子注入能量的多个离子注入步骤中掺杂沟槽MOSFET的体区。 该方法还包括将沟槽蚀刻至约1.7μm的深度。