公开(公告)号：US20130193506A1

公开(公告)日：2013-08-01

申请号：US13362697

申请日：2012-01-31

申请人： SUNG-TAEG KANG ,  GOWRISHANKAR L. CHINDALORE ,  BRIAN A. WINSTEAD ,  JANE A. YATER

发明人： SUNG-TAEG KANG ,  GOWRISHANKAR L. CHINDALORE ,  BRIAN A. WINSTEAD ,  JANE A. YATER

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42332

摘要： A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.

摘要翻译： 一种形成半导体器件的方法包括在具有第一区域和第二区域的衬底的表面上形成第一多个纳米晶体，其中所述第一多个纳米晶体形成在所述第一区域和所述第二区域中，并具有第一密度 ; 并且在形成所述第一多个纳米晶体之后，在所述第二区域而不是所述第一区域的所述衬底的表面上形成第二多个纳米晶体，其中所述第一多个纳米晶体与所述第二区域中的所述第二多个纳米晶体结果 在第二密度中，其中第二密度大于第一密度。

公开(公告)号：US20120126309A1

公开(公告)日：2012-05-24

申请号：US12951862

申请日：2010-11-22

申请人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

发明人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

IPC分类号： H01L29/68 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

摘要： A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.

摘要翻译： 在NVM器件和逻辑器件的图案化和蚀刻期间，在NVM隔离区域中形成特征，使得该特征与逻辑器件的高度基本相等，并且被明确地限定，使得其不会引起缺陷信号。 第一导电层形成在衬底上。 图案化第一导电层以在NVM区域和隔离区域的至少一部分中露出衬底的至少一部分。 在第一导电层，暴露的衬底和暴露的隔离区上方形成NVM电介质堆叠，并且在NVM电介质叠层上形成第二导电层。 图案化第一和第二导电层和NVM电介质叠层以形成NVM区域中的NVM单元的第一栅极和第二栅极以及隔离区域上的特征。 该特征包括第一导电层的一部分，与第一导电层的该部分的第一侧壁相邻的NVM电介质堆叠的一部分以及邻近NVM电介质叠层部分的第二导电层的一部分。

公开(公告)号：US20150001612A1

公开(公告)日：2015-01-01

申请号：US13928666

申请日：2013-06-27

申请人： CHEONG MIN HONG ,  SUNG-TAEG KANG ,  JANE A. YATER

发明人： CHEONG MIN HONG ,  SUNG-TAEG KANG ,  JANE A. YATER

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。