公开(公告)号：US20150179816A1

公开(公告)日：2015-06-25

申请号：US14135142

申请日：2013-12-19

申请人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

发明人： JACOB T. WILLIAMS ,  Cheong Min Hong ,  Sung-Taeg Kang ,  David G. Kolar ,  Jane A. Yater

IPC分类号： H01L29/792 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/66

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

摘要翻译： 形成闪存单元的方法包括在基板上形成第一硬掩模和第二硬掩模。 选择栅极形成为围绕第一硬掩模的间隔物。 在第一和第二硬掩模和选择栅极上形成电荷存储层。 控制栅极形成为围绕第二硬掩模的间隔物。 控制栅极中的凹槽填充有电介质材料。 凹槽形成在控制栅极的弯曲侧壁和电荷存储层的与控制栅极的弯曲侧壁直接相邻的侧壁之间。

公开(公告)号：US09006093B2

公开(公告)日：2015-04-14

申请号：US13928666

申请日：2013-06-27

申请人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

发明人： Cheong Min Hong ,  Sung-Taeg Kang ,  Jane A. Yater

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.

摘要翻译： 制造半导体结构的方法包括在衬底上形成选择栅叠层。 衬底包括非易失性存储器（NVM）区域和高电压区域。 选择栅极堆叠形成在NVM区域中。 电荷存储层形成在衬底的NVM区域和高电压区域上。 电荷存储层包括在介电材料的底层和电介质材料的顶层之间的电荷存储材料。 在NVM区域中的电荷存储材料保持未氧化的同时，高压区域中的电荷存储材料被氧化。

公开(公告)号：US08877585B1

公开(公告)日：2014-11-04

申请号：US13969180

申请日：2013-08-16

申请人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

发明人： Asanga H. Perera ,  Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/11546 ,  H01L29/42332 ,  H01L29/66825

摘要： A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.

摘要翻译： 使用具有非易失性存储器（NVM）部分，第一高压部分，第二高压部分和逻辑部分的衬底制造半导体结构的方法包括在主要的氧化物层上形成第一导电层 NVM部分中的衬底表面，第一和第二高压部分以及逻辑部分。 在NVM部分中制造存储单元，同时第一导电层保留在第一和第二高压部分和逻辑部分中。 图案化第一导电层以在第一和第二高压部分中形成晶体管栅极。 在NVM部分和第一和第二高压部分上形成保护掩模。 晶体管栅极形成在逻辑部分中，同时保护掩模保留在NVM部分以及第一和第二高电压部分中。

公开(公告)号：US20140209995A1

公开(公告)日：2014-07-31

申请号：US13753047

申请日：2013-01-29

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced.

摘要翻译： 公开了具有碳杂质的非易失性存储器（NVM）单元以及相关的制造方法。 可以使用各种技术引入碳杂质，包括通过硅 - 碳（SiC）层和/或碳植入物的外延生长。 此外，可以将碳杂质引入NVM单元内的一个或多个结构，包括源极区，漏极区，栅极区和/或电荷存储层。 对于利用纳米晶体结构的离散电荷存储层，可将碳杂质引入纳米晶电荷存储层。 所公开的实施例对于包括分裂门NVM单元，浮动栅极NVM单元，分立电荷存储NVM单元和/或其它期望的NVM单元的各种NVM单元类型是有用的。 有利地，碳杂质将细胞结构中的拉伸应力引入，并且即使在减小器件几何形状的情况下，该拉伸应力有助于维持NVM系统性能和数据保持。

公开(公告)号：US08778742B1

公开(公告)日：2014-07-15

申请号：US13871411

申请日：2013-04-26

申请人： Sung-Taeg Kang ,  ShanShan Du

发明人： Sung-Taeg Kang ,  ShanShan Du

IPC分类号： H01L21/82

CPC分类号： H01L27/11563 ,  H01L21/823437 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： Methods and systems are disclosed for gate dimension control in multi-gate structures for integrated circuit devices. Processing steps for formation of one or more subsequent gate structures are adjusted based upon dimensions determined for one or more previously formed gate structures. In this way, one or more features of the resulting multi-gate structures can be controlled with greater accuracy, and variations between a plurality of multi-gate structures can be reduced. Example multi-gate features and/or dimensions that can be controlled include overall gate length, overlap of gate structures, and/or any other desired features and/or dimensions of the multi-gate structures. Example multi-gate structures include multi-gate NVM (non-volatile memory) cells for NVM systems, such as for example, split-gate NVM cells having select gates (SGs) and control gates (CGs).

摘要翻译： 公开了用于集成电路器件的多栅极结构中的栅极尺寸控制的方法和系统。 基于为一个或多个先前形成的栅极结构确定的尺寸来调整用于形成一个或多个后续栅极结构的处理步骤。 以这种方式，可以以更高的精度控制所得到的多栅极结构的一个或多个特征，并且可以减少多个多栅极结构之间的变化。 可以控制的示例性多栅极特征和/或尺寸包括整个栅极长度，栅极结构的重叠和/或多栅极结构的任何其它期望特征和/或尺寸。 示例性多栅极结构包括用于NVM系统的多栅极NVM（非易失性存储器）单元，例如具有选择栅极（SG）和控制栅极（CG）的分离栅极NVM单元。

公开(公告)号：US20140003155A1

公开(公告)日：2014-01-02

申请号：US13536307

申请日：2012-06-28

申请人： CHEONG MIN HONG ,  Sung-Taeg Kang

发明人： CHEONG MIN HONG ,  Sung-Taeg Kang

IPC分类号： G11C16/10

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/3459

摘要： A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.

摘要翻译： 用于对分割门存储器单元进行编程的方法包括在分离栅极存储单元的第一编程周期中执行分离栅极存储单元的第一编程; 并且在执行所述分离栅极存储器单元的第一编程之后，在所述第一编程周期中执行所述分离栅极存储单元的第二编程，其中所述第一编程被表征为源侧注入（SSI）编程之一， 通道启动的二次电子（CHISEL）编程，第二个编程被表征为SSI编程和CHISEL编程中的另一个。

公开(公告)号：US20120126309A1

公开(公告)日：2012-05-24

申请号：US12951862

申请日：2010-11-22

申请人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

发明人： JANE A. YATER ,  Sung-Taeg Kang ,  Mehul D. Shroff

IPC分类号： H01L29/68 ,  H01L21/28

CPC分类号： H01L27/105 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/788 ,  H01L29/792

摘要： A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.

摘要翻译： 在NVM器件和逻辑器件的图案化和蚀刻期间，在NVM隔离区域中形成特征，使得该特征与逻辑器件的高度基本相等，并且被明确地限定，使得其不会引起缺陷信号。 第一导电层形成在衬底上。 图案化第一导电层以在NVM区域和隔离区域的至少一部分中露出衬底的至少一部分。 在第一导电层，暴露的衬底和暴露的隔离区上方形成NVM电介质堆叠，并且在NVM电介质叠层上形成第二导电层。 图案化第一和第二导电层和NVM电介质叠层以形成NVM区域中的NVM单元的第一栅极和第二栅极以及隔离区域上的特征。 该特征包括第一导电层的一部分，与第一导电层的该部分的第一侧壁相邻的NVM电介质堆叠的一部分以及邻近NVM电介质叠层部分的第二导电层的一部分。

公开(公告)号：US08163609B2

公开(公告)日：2012-04-24

申请号：US12964727

申请日：2010-12-09

申请人： Cheong Min Hong ,  Sung-Taeg Kang

发明人： Cheong Min Hong ,  Sung-Taeg Kang

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02601 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/7881

摘要： A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

摘要翻译： 使用半导体衬底制造半导体器件的方法包括在半导体衬底上形成具有第一带能的第一绝缘层。 具有第二带能的第一半导体层形成在第一绝缘层上。 第一半导体层被退火以从第一半导体层形成多个第一电荷保持器球。 在多个第一电荷保持器球的每个电荷保持器球上形成第一保护膜。 在多个第一电荷保持器球上形成具有第三带能的第二半导体层。 第二半导体层被退火以在多个第一电荷保持器球上从第二半导体层形成多个存储小球。 第二带能量的大小在第一带能量的大小和第三带能量的大小之间。

公开(公告)号：US07957190B2

公开(公告)日：2011-06-07

申请号：US12130197

申请日：2008-05-30

申请人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

发明人： Cheong M. Hong ,  Sung-Taeg Kang ,  Brian A. Winstead

IPC分类号： G11C16/04

CPC分类号： G11C16/0425

摘要： A memory comprising a plurality of P-channel split-gate memory cells are organized in rows and columns. Each of the plurality of P-channel split-gate memory cells comprises a select gate, a control gate, a source region, a drain region, a channel region, and a charge storage layer comprising nanocrystals. Programming a memory cell of the plurality of P-channel split-gate memory cells comprises injecting electrons from a channel region of the memory cell to the charge storage layer. Erasing the memory cell comprises injecting holes from the channel region to the charge storage region.

摘要翻译： 包括多个P沟道分裂门存储器单元的存储器以行和列组织。 多个P沟道分离栅极存储单元中的每一个包括选择栅极，控制栅极，源极区域，漏极区域，沟道区域和包含纳米晶体的电荷存储层。 编程多个P沟道分离栅极存储单元的存储单元包括将电子从存储单元的沟道区域注入电荷存储层。 擦除存储单元包括从通道区域向电荷存储区域注入空穴。

公开(公告)号：US07799634B2

公开(公告)日：2010-09-21

申请号：US12339262

申请日：2008-12-19

申请人： Jinmiao J. Shen ,  Horacio P. Gasquet ,  Sung-Taeg Kang ,  Marc A. Rossow

发明人： Jinmiao J. Shen ,  Horacio P. Gasquet ,  Sung-Taeg Kang ,  Marc A. Rossow

IPC分类号： H01L21/336

CPC分类号： H01L21/02532 ,  B82Y10/00 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/28273 ,  H01L21/28282

摘要： Nanocrystals are formed over an insulating layer by depositing a semiconductor layer over the insulating layer. The semiconductor layer is annealed to form a plurality of globules from the semiconductor layer. The globules are annealed using oxygen. Semiconductor material is deposited on the plurality of globules to add semiconductor material to the globules. After depositing the semiconductor material, the globules are annealed to form the nanocrystals. The nanocrystals can then be used in a storage layer of a non-volatile memory cell, especially a split-gate non-volatile memory cell having a select gate over the nanocrystals and a control gate adjacent to the select gate.

摘要翻译： 通过在绝缘层上沉积半导体层，在绝缘层上形成纳米晶体。 将半导体层退火以从半导体层形成多个球。 使用氧气对小球进行退火。 半导体材料沉积在多个小球上以将半导体材料加入到球体中。 在沉积半导体材料之后，将小球退火以形成纳米晶体。 然后可以将纳米晶体用于非易失性存储单元的存储层，特别是在纳米晶体上具有选择栅极的分离栅非易失性存储单元和与选择栅极相邻的控制栅极。