公开(公告)号：US20220028886A1

公开(公告)日：2022-01-27

申请号：US17382126

申请日：2021-07-21

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Yosuke Nosho ,  Shohei Kamisaka ,  Michiru Nakane ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/51 ,  H01L21/28

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

公开(公告)号：US20230247831A9

公开(公告)日：2023-08-03

申请号：US17382126

申请日：2021-07-21

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Yosuke Nosho ,  Shohei Kamisaka ,  Michiru Nakane ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L29/513 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/517

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.

公开(公告)号：US11751391B2

公开(公告)日：2023-09-05

申请号：US17382126

申请日：2021-07-21

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Vinod Purayath ,  Yosuke Nosho ,  Shohei Kamisaka ,  Michiru Nakane ,  Eli Harari

IPC: H01L21/28 ,  H10B43/27 ,  H01L29/51

CPC classification number: H10B43/27 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.