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    System and method for reservation station load dependency matrix
    1.
    发明授权
    System and method for reservation station load dependency matrix 有权
    保留站负载依赖矩阵的系统和方法

    公开(公告)号：US07958336B2

    公开(公告)日：2011-06-07

    申请号：US12164666

    申请日：2008-06-30

    申请人： Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    发明人： Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    摘要翻译： 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX
    2.
    发明申请
    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX 有权
    用于预留站负载依赖矩阵的系统和方法

    公开(公告)号：US20090328057A1

    公开(公告)日：2009-12-31

    申请号：US12164666

    申请日：2008-06-30

    申请人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    发明人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/445

    CPC分类号： G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    摘要翻译： 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

    GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)
    3.
    发明申请
    GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops) 审中-公开
    生成和执行包含多个微操作的依赖性控制流（uop）

    公开(公告)号：US20090327657A1

    公开(公告)日：2009-12-31

    申请号：US12146390

    申请日：2008-06-25

    申请人： Zeev Sperber ,  Sagi Lahav ,  Guy Patkin ,  Simon Rubanovich ,  Amit Gradstein ,  Yuval Bustan

    发明人： Zeev Sperber ,  Sagi Lahav ,  Guy Patkin ,  Simon Rubanovich ,  Amit Gradstein ,  Yuval Bustan

    IPC分类号： G06F9/22

    CPC分类号： G06F9/3836 ,  G06F9/3017 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3853

    摘要： A processor to perform an out-of-order (OOO) processing in which a reservation station (RS) may generate and process a dependency controlled flow comprising multiple micro-operations (uops) with specific clock based dispatch scheme. The RS may either combine two or more uops into a single RS entry or make a direct connection between two or more RS entries. The RS may allow more than two source values to be associated with a single RS by combining sources from the two or more uops. One or more execution units may be provisioned to perform the function defined by the uops. The execution units may receive more than two sources at a given time point and produce two or more results on different ports.

    摘要翻译： 执行无序（OOO）处理的处理器，其中保留站（RS）可以生成并处理包括具有特定的基于时钟的调度方案的多个微操作（uop）的依赖性控制流。 RS可以将两个或更多个uops组合成单个RS条目，或者在两个或更多个RS条目之间建立直接连接。 RS可以通过组合来自两个或更多个uops的源来允许多于两个源值与单个RS相关联。 可以提供一个或多个执行单元来执行由uops定义的功能。 执行单元可以在给定的时间点接收多于两个的源，并且在不同端口上产生两个或更多个结果。

    Processor and methods to reduce power consumption of processor components
    4.
    发明申请
    Processor and methods to reduce power consumption of processor components 审中-公开

    公开(公告)号：US20070088965A1

    公开(公告)日：2007-04-19

    申请号：US11637064

    申请日：2006-12-12

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    Apparatus and methods for utilization of splittable execution units of a processor
    6.
    发明申请
    Apparatus and methods for utilization of splittable execution units of a processor 有权
    利用处理器的可分割执行单元的装置和方法

    公开(公告)号：US20060095740A1

    公开(公告)日：2006-05-04

    申请号：US10950690

    申请日：2004-09-28

    申请人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

    发明人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3857 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867 ,  G06F9/3887

    摘要： A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

    摘要翻译： 可拆分执行单元的部分执行单元对微操作的一个或多个参数的一部分执行操作，以产生微操作的第一部分执行结果。 其中一个参数的补充部分通过旁路执行单元而不是通过可分割执行单元传递，以生成微操作的第二部分执行结果。 第一部分执行结果和第二部分执行结果被连接成一个完整的执行结果。

    Processor and methods to reduce power consumption of processor components
    7.
    发明授权
    Processor and methods to reduce power consumption of processor components 失效
    处理器和方法来降低处理器组件的功耗

    公开(公告)号：US07167989B2

    公开(公告)日：2007-01-23

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F9/00

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下运行，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。

    Apparatus and methods for utilization of splittable execution units of a processor
    8.
    发明授权
    Apparatus and methods for utilization of splittable execution units of a processor 有权
    利用处理器的可分割执行单元的装置和方法

    公开(公告)号：US07389406B2

    公开(公告)日：2008-06-17

    申请号：US10950690

    申请日：2004-09-28

    申请人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

    发明人： Zeev Sperber ,  Guillermo Savransky ,  Sagi Lahav

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3857 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3867 ,  G06F9/3887

    摘要： A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed through a bypass execution unit instead of through the splittable execution unit to generate a second partial execution result of the micro-operation. The first partial execution result and second partial execution result are concatenated into a full execution result.

    摘要翻译： 可拆分执行单元的部分执行单元对微操作的一个或多个参数的一部分执行操作，以产生微操作的第一部分执行结果。 其中一个参数的补充部分通过旁路执行单元而不是通过可分割执行单元传递，以生成微操作的第二部分执行结果。 第一部分执行结果和第二部分执行结果被连接成一个完整的执行结果。

    Processor and methods to reduce power consumption of procesor components
    10.
    发明申请
    Processor and methods to reduce power consumption of procesor components 失效
    处理器和减少处理器组件功耗的方法

    公开(公告)号：US20050081067A1

    公开(公告)日：2005-04-14

    申请号：US10682892

    申请日：2003-10-14

    申请人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    发明人： Zeev Sperber ,  Ittai Anati ,  Ofer Sierra ,  Asi Joseph ,  Sagi Lahav

    IPC分类号： G06F1/32 ,  G06F1/26

    CPC分类号： G06F1/3228 ,  G06F1/3203

    摘要： Periods of futile activity by one or more logic circuits of a component of a processor may be predicted, and then during each such period, one or more of the logic circuits may operate in a power-save state with reduced power consumption, with the latter part of the period being used to bring the logic circuits back into performance state, so that performance is not diminished beyond an acceptable level due to the power-save state. The decision of whether to reduce the power consumption of a particular logic circuit of a particular processor component is to have at a particular future time is made internally in the particular processor component based on one or more signals received by the particular processor component.

    摘要翻译： 可以预测处理器的部件的一个或多个逻辑电路的无效活动的周期，然后在每个这样的周期期间，一个或多个逻辑电路可以以降低的功耗在功率节省状态下工作，后者 用于使逻辑电路恢复到执行状态的一部分时间段，使得由于省电状态，性能不会降低到超出可接受的水平。 基于由特定处理器组件接收的一个或多个信号，在特定处理器组件内部是否在特定未来时间内进行降低特定处理器组件的特定逻辑电路的功耗的决定。