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    Serial Advanced Technology Attachment (SATA) switch
    1.
    发明授权
    Serial Advanced Technology Attachment (SATA) switch 有权
    串行高级技术附件（SATA）开关

    公开(公告)号：US07523235B2

    公开(公告)日：2009-04-21

    申请号：US10775488

    申请日：2004-02-09

    申请人： Sam Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Siamack Nemazie ,  Andrew Hyonil Chong

    发明人： Sam Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Siamack Nemazie ,  Andrew Hyonil Chong

    IPC分类号： G06F13/12 ,  G06F13/38

    CPC分类号： G06F13/4022

    摘要： A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

    摘要翻译： 开关耦合在多个主机单元和用于在它们之间通信的装置。 包括第一个串行高级技术附件（SATA）端口，第二个SATA端口和第三个SATA端口。 第一SATA端口包括耦合到第一主机单元的第一主机任务文件，并且第一主机任务文件响应于由第一主机单元发送到设备的命令。 第二SATA端口包括耦合到第二主机单元的第二主机任务文件，并且第二主机任务文件响应于由第二主机单元发送到设备的命令。 仲裁控制电路耦合到SATA端口，并且通过交换机从第一和第二主机中选择同时访问设备，在任何时候接收来自主机单元的命令，包括何时设备不空闲。

    High performance architecture for fiber channel targets and target bridges
    5.
    发明授权
    High performance architecture for fiber channel targets and target bridges 失效
    光纤通道目标和目标桥梁的高性能架构

    公开(公告)号：US07986630B1

    公开(公告)日：2011-07-26

    申请号：US11165713

    申请日：2005-06-24

    申请人： Siamack Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Andrew Hyonil Chong

    发明人： Siamack Nemazie ,  Shiang-Jyh Chang ,  Young-Ta Wu ,  Andrew Hyonil Chong

    IPC分类号： G01R31/08

    CPC分类号： G06F13/4247 ,  G06F2213/0032

    摘要： An embodiment of the present invention is disclosed to include a fiber channel target device for receiving information in the form of frames and including a controller device coupled to a microprocessor for processing the frames received from the host, at least one receive buffer for storing the frames and having a buffer size, the controller device issuing credit to the host for receipt of further frames in a manner wherein only one microprocessor is needed to process the frames while maintaining a buffer size that is as small as the number of first type of frames that can be received by the fiber channel target device from the host.

    摘要翻译： 公开了本发明的一个实施例，其包括用于以帧的形式接收信息的光纤通道目标设备，并且包括耦合到微处理器的控制器设备，用于处理从主机接收的帧，至少一个用于存储帧的接收缓冲器 并且具有缓冲器大小，所述控制器设备向所述主机发出信用以接收另外的帧，其中只需要一个微处理器来处理所述帧，同时保持与第一类型的帧的数量一样小的缓冲器大小， 可由光纤通道目标设备从主机接收。

    Route aware Serial Advanced Technology Attachment (SATA) Switch
    8.
    发明授权
    Route aware Serial Advanced Technology Attachment (SATA) Switch 有权
    路由感知串行高级技术附件（SATA）开关

    公开(公告)号：US07539797B2

    公开(公告)日：2009-05-26

    申请号：US10775523

    申请日：2004-02-09

    申请人： Siamack Nemazie ,  Andrew Hyonil Chong

    发明人： Siamack Nemazie ,  Andrew Hyonil Chong

    IPC分类号： G06F13/12 ,  G06F13/38

    CPC分类号： G06F13/4022

    摘要： A switch is coupled between a plurality of host units and a device for routing frame information therebetween. The switch includes a first serial advanced technology attachment (ATA) port including a first host task file that is responsive to a non-data frame information structure (FIS) from a first host unit. The switch further includes a second serial ATA port including a second host task file that is responsive to a non-data FIS from a second host unit. The switch further includes a third serial ATA port that is responsive to a non-data FIS from a device and further includes an arbitration and control circuit for selecting one of the first host or second host units to concurrently access the device, through the switch, by accepting non-data FIS, from either of the first or second host units, at any given time, including when the device is not in an idle state.

    摘要翻译： 交换机耦合在多个主机单元和用于在其间路由帧信息的设备。 交换机包括第一串行高级技术附件（ATA）端口，其包括响应于来自第一主机单元的非数据帧信息结构（FIS）的第一主机任务文件。 交换机还包括第二串行ATA端口，其包括响应于来自第二主机单元的非数据FIS的第二主机任务文件。 该交换机还包括响应来自设备的非数据FIS的第三串行ATA端口，并且还包括仲裁和控制电路，用于通过交换机选择第一主机或第二主机单元中的一个并发访问设备， 通过在任何给定的时间，包括当设备不处于空闲状态时从第一或第二主机单元中的任一个接收非数据FIS。

    Integrated disc drive controller
    9.
    发明授权
    Integrated disc drive controller 有权
    集成磁盘驱动器控制器

    公开(公告)号：US07475173B2

    公开(公告)日：2009-01-06

    申请号：US11378456

    申请日：2006-03-17

    申请人： Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

    发明人： Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

    IPC分类号： G06F13/00

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G06F3/0676 ,  G11B19/00 ,  G11B20/10009 ,  G11B25/043

    摘要： An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

    摘要翻译： 集成数据存储控制系统在单一集成电路中提供RDC，伺服逻辑，ATA接口，微处理器以及其它以前分立的组件，在一个高度集成的系统设计中。 使用针对所有组件的单个集成电路技术类型（例如，数字CMOS）来呈现集成电路。 模拟和数字电路的组合方式是消除或减少模拟电路组件在数字电路中的噪声或干扰。 单个元件可以将它们的输出和输入多路复用在一起，使得各个元件可以选择性地切换（在测试模式期间），使得集成电路以与现有技术组件中的一个相同或相似的方式进行仿真或表现。 本发明可以应用于磁性硬盘驱动器（HDD）或诸如软盘控制器，光盘驱动器（例如CD-ROM等），磁带驱动器和其他数据存储设备的其它类型的存储设备。