公开(公告)号：US20070232041A1

公开(公告)日：2007-10-04

申请号：US11510058

申请日：2006-08-25

申请人： Sam-jong Choi ,  Kyoo-chul Cho ,  Soo-yeol Choi ,  Yong-kwon Kim ,  Young-soo Park ,  Chan-kook In ,  Hae-jin Park ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Kyoo-chul Cho ,  Soo-yeol Choi ,  Yong-kwon Kim ,  Young-soo Park ,  Chan-kook In ,  Hae-jin Park ,  Sang-Sig Kim

IPC分类号： H01L21/3205

CPC分类号： H01L21/265 ,  B82Y10/00 ,  G11C2216/06 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7885 ,  H01L29/7887

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a metal oxide dielectric layer on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the dielectric layer to form a charge storing region in the dielectric layer with a tunnel dielectric layer under the charge storing region and a capping dielectric layer above the charge storing region. The substrate including the metal oxide dielectric layer is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region. A gate electrode layer is formed on the dielectric layer.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成金属氧化物介电层。 将元素周期表第4组的选定元素的离子注入到电介质层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，形成电荷存储区 在具有电荷存储区域下方的隧道介电层的电介质层和电荷存储区域上方的封盖电介质层。 包含金属氧化物介电层的基板被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体。 在电介质层上形成栅极电极层。

公开(公告)号：US07550347B2

公开(公告)日：2009-06-23

申请号：US11510059

申请日：2006-08-25

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区， 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US20070128846A1

公开(公告)日：2007-06-07

申请号：US11510059

申请日：2006-08-25

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储 区域，在电荷存储区域下方具有隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US20090236655A1

公开(公告)日：2009-09-24

申请号：US12468414

申请日：2009-05-19

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US07964907B2

公开(公告)日：2011-06-21

申请号：US12468414

申请日：2009-05-19

申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

公开(公告)号：US20090114904A1

公开(公告)日：2009-05-07

申请号：US12347591

申请日：2008-12-31

申请人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

发明人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

IPC分类号： H01L29/66

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0558

摘要： A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

摘要翻译： 半导体器件包括衬底，衬底上的栅电极和设置在栅电极的相应侧的源电极和漏电极。 该器件还包括通过栅电极并延伸到源电极和漏极并具有半导体特性的纳米线。 纳米线可以包括纳米线和/或纳米管。 栅极绝缘层可以插入在纳米线和栅电极之间。 源电极和漏电极可以邻近栅电极的相对侧壁设置，并且栅极绝缘层可以进一步插入在源电极和漏电极与栅电极之间。 还描述了这种装置的制造方法。

公开(公告)号：US07482206B2

公开(公告)日：2009-01-27

申请号：US11422663

申请日：2006-06-07

申请人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

发明人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

IPC分类号： H01L21/335

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0558

摘要： A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

摘要翻译： 半导体器件包括衬底，衬底上的栅电极和设置在栅电极的相应侧的源电极和漏电极。 该器件还包括通过栅电极并延伸到源电极和漏极并具有半导体特性的纳米线。 纳米线可以包括纳米线和/或纳米管。 栅极绝缘层可以插入在纳米线和栅电极之间。 源电极和漏电极可以邻近栅电极的相对侧壁设置，并且栅极绝缘层可以进一步插入在源电极和漏电极与栅电极之间。 还描述了这种装置的制造方法。

公开(公告)号：US20070072335A1

公开(公告)日：2007-03-29

申请号：US11422663

申请日：2006-06-07

申请人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

发明人： Seung-Jae Baik ,  In-Seok Yeo ,  Sang-Sig Kim ,  Ki-Hyun Kim ,  Dong-Young Jeong

IPC分类号： H01L51/40 ,  H01L29/76 ,  H01L29/745

CPC分类号： H01L51/0508 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0558

摘要： A semiconductor device includes a substrate, a gate electrode on the substrate and source and drain electrodes disposed at respective sides of the gate electrode. The device further includes a nano-line passing through the gate electrode and extending into the source and drain electrodes and having semiconductor characteristics. The nano-line may include a nano-wire and/or a nano-tube. A gate insulating layer may be interposed between the nano-line and the gate electrode. The source and drain electrodes may be disposed adjacent respective opposite sidewalls of the gate electrode, and the gate insulating layer may be further interposed between the source and drain electrodes and the gate electrode. Fabrication methods for such devices are also described.

摘要翻译： 半导体器件包括衬底，衬底上的栅电极和设置在栅电极的相应侧的源电极和漏电极。 该器件还包括通过栅电极并延伸到源电极和漏极并具有半导体特性的纳米线。 纳米线可以包括纳米线和/或纳米管。 栅极绝缘层可以插入在纳米线和栅电极之间。 源电极和漏电极可以邻近栅电极的相对侧壁设置，并且栅极绝缘层可以进一步插入在源电极和漏电极与栅电极之间。 还描述了这种装置的制造方法。