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    Methods of forming integrated circuit device gate structures
    2.
    发明授权
    Methods of forming integrated circuit device gate structures 有权
    形成集成电路器件门结构的方法

    公开(公告)号：US07550347B2

    公开(公告)日：2009-06-23

    申请号：US11510059

    申请日：2006-08-25

    申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区， 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    Integrated circuit device gate structures and methods of forming the same
    3.
    发明申请
    Integrated circuit device gate structures and methods of forming the same 有权
    集成电路器件栅极结构及其形成方法

    公开(公告)号：US20070128846A1

    公开(公告)日：2007-06-07

    申请号：US11510059

    申请日：2006-08-25

    申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储 区域，在电荷存储区域下方具有隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    Integrated circuit device gate structures
    4.
    发明授权
    Integrated circuit device gate structures 有权
    集成电路器件门结构

    公开(公告)号：US07964907B2

    公开(公告)日：2011-06-21

    申请号：US12468414

    申请日：2009-05-19

    申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    INTEGRATED CIRCUIT DEVICE GATE STRUCTURES
    5.
    发明申请
    INTEGRATED CIRCUIT DEVICE GATE STRUCTURES 有权
    集成电路设计门结构

    公开(公告)号：US20090236655A1

    公开(公告)日：2009-09-24

    申请号：US12468414

    申请日：2009-05-19

    申请人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    发明人： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    摘要： Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    摘要翻译： 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    3D CMOS image sensors, sensor systems including the same
    6.
    发明授权
    3D CMOS image sensors, sensor systems including the same 有权
    3D CMOS图像传感器，传感器系统包括相同

    公开(公告)号：US09035309B2

    公开(公告)日：2015-05-19

    申请号：US12984972

    申请日：2011-01-05

    申请人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    发明人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14629 ,  H01L27/14687

    摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

    摘要翻译： 一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺 包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。

    3D CMOS Image Sensors, Sensor Systems Including the Same
    7.
    发明申请
    3D CMOS Image Sensors, Sensor Systems Including the Same 有权
    3D CMOS图像传感器，包括它的传感器系统

    公开(公告)号：US20110193940A1

    公开(公告)日：2011-08-11

    申请号：US12984972

    申请日：2011-01-05

    申请人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    发明人： Young-soo Park ,  Won-joo Kim ,  Kyoo-chul Cho ,  Gi-jung Kim ,  Sam-jong Choi

    IPC分类号： H04N13/02 ,  H01L27/146

    CPC分类号： H01L27/14629 ,  H01L27/14687

    摘要： A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

    摘要翻译： 一种三维（3D）CMOS图像传感器（CIS），其足以吸收入射的红外线（IR）并且包括形成在薄的外延膜中的红外线（IR）接收单元，由此容易地使用传统的CIS工艺 包括3D CIS的传感器系统和制造3D CIS的方法，3D CIS包括通过重复反射吸收入射到其中的IR的IR接收部分以产生电子 - 空穴对（EHP）; 以及形成在IR接收部上并且收集通过施加预定电压而产生的电子的电极部分。