公开(公告)号：US20220269534A1

公开(公告)日：2022-08-25

申请号：US17185264

申请日：2021-02-25

Applicant: SambaNova Systems, Inc.

Inventor： Anand MISRA ,  Arnav GOEL ,  Qi ZHENG ,  Raghunath SHENBAGAM ,  Ravinder KUMAR

IPC: G06F9/48 ,  G06F9/38

Abstract: A method for executing applications in a system comprising general hardware and reconfigurable hardware includes accessing a first execution file comprising metadata storing a first priority indicator associated with a first application, and a second execution file comprising metadata storing a second priority indicator associated with a second application. In an example, use of the reconfigurable hardware is interleaved between the first application and the second application, and the interleaving is scheduled to take into account (i) workload of the reconfigurable hardware and (ii) the first priority indicator and the second priority indicator associated with the first application and the second application, respectively. In an example, when the reconfigurable hardware is used by one of the first and second applications, the general hardware is used by another of the first and second applications.

公开(公告)号：US20220308935A1

公开(公告)日：2022-09-29

申请号：US17528081

申请日：2021-11-16

Applicant: SambaNova Systems, Inc.

Inventor： Raghunath SHENBAGAM ,  Ravinder KUMAR

IPC: G06F9/50 ,  G06F9/445 ,  H04L47/28 ,  G06F9/455 ,  G06F15/78

Abstract: The technology disclosed relates to interconnect-based resource allocation for reconfigurable processors. In particular, the technology disclosed relates to a runtime logic that is configured to receive target interconnect bandwidth and target interconnect latency, and rated interconnect bandwidth and rated interconnect latency. The runtime logic is further configured to respond by allocating, to configuration files defining an application graph, processing elements in a plurality of processing elements, and interconnects between the processing elements, and executing the configuration files using the allocated processing elements and the allocated interconnects.

公开(公告)号：US20240264896A1

公开(公告)日：2024-08-08

申请号：US18105777

申请日：2023-02-03

Applicant: SambaNova Systems, Inc.

Inventor： Raghunath SHENBAGAM ,  Ranen CHATTERJEE ,  Anand MISRA ,  Jim LEWIS ,  Benjamin GLICK ,  Pushkar NANDKAR ,  Sruthi VEERAGANDHAM

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F11/0769

Abstract: A fault management system (FMS) receives events indicating an issue with a component in the system and determines, based on an inventory database, the component associated with the events. The FMS creates, based at least in part on the events, an error report that includes: (i) an error type identifying a type of error described in the error report, (ii) a timestamp indicating when the error report was created, and (iii) a universal unique identifier (UUID) to uniquely identify the error report. The FMS determines, based at least in part on the error report, a policy associated with the events and classifies the events, based at least in part on the policy, as either a threshold event or a discrete event. The FMS performs one or more actions to address the events.

公开(公告)号：US20230205585A1

公开(公告)日：2023-06-29

申请号：US18084013

申请日：2022-12-19

Applicant: SambaNova Systems, Inc.

Inventor： Ranen CHATTERJEE ,  Ravinder KUMAR ,  Raghunath SHENBAGAM ,  Maran WILSON ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Arjun SABNIS ,  Yannan CHEN

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F13/40

CPC classification number: G06F9/5016 ,  G06F9/545 ,  G06F9/30123 ,  G06F13/4059 ,  G06F2209/5011

Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.

公开(公告)号：US20240330074A1

公开(公告)日：2024-10-03

申请号：US18740240

申请日：2024-06-11

Applicant: SambaNova Systems, Inc.

Inventor： Raghunath SHENBAGAM ,  Ravinder KUMAR

IPC: G06F9/50 ,  G06F9/445 ,  G06F9/455 ,  G06F15/78 ,  H04L41/0896 ,  H04L47/28

CPC classification number: G06F9/5077 ,  G06F9/44505 ,  G06F9/45558 ,  G06F9/5044 ,  G06F15/7892 ,  H04L47/28 ,  G06F2009/4557 ,  G06F2009/45595 ,  G06F2209/5011 ,  G06F2213/0062 ,  G06F2213/0064 ,  H04L41/0896

Abstract: The disclosed technology relates to link-based resource allocation for a pool of reconfigurable processors. Resource allocation is provided for reconfigurable processors based on link bandwidths and link latencies. Runtime logic receives target link bandwidth and target link latency and rated link bandwidth and rated link latency. In response, the runtime logic allocates configuration files for an application, reconfigurable processors, and links between the processors. The runtime logic executes the allocated configuration files using the allocated processors and the allocated links. In another embodiment, the pool of reconfigurable processors comprise a cluster of processing nodes connected through a network.

公开(公告)号：US20230409395A1

公开(公告)日：2023-12-21

申请号：US18211962

申请日：2023-06-20

Applicant: SambaNova Systems, Inc.

Inventor： Ravinder KUMAR ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Qi ZHENG ,  Raghunath SHENBAGAM ,  Anand MISRA ,  Ananda Reddy VAYYALA

IPC: G06F9/50 ,  G06F15/78

CPC classification number: G06F9/5011 ,  G06F9/5016 ,  G06F15/7871 ,  G06F15/7867 ,  G06F9/5077 ,  G06F2209/501 ,  G06F2209/5011

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

公开(公告)号：US20220012077A1

公开(公告)日：2022-01-13

申请号：US16922975

申请日：2020-07-07

Applicant: SambaNova Systems, Inc.

Inventor： Ravinder KUMAR ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Qi ZHENG ,  Raghunath SHENBAGAM ,  Anand MISRA ,  Ananda Reddy VAYYALA

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/54 ,  G06F13/16 ,  G06F12/10

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.