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1.发明授权Method of fabricating a device using low temperature anneal processes, a device and design structure 有权使用低温退火工艺制造器件的方法，器件和设计结构公开(公告)号：US08490029B2
公开(公告)日：2013-07-16
申请号：US13421400
申请日：2012-03-15
申请人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。
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2.发明授权Method of fabricating a device using low temperature anneal processes, a device and design structure 有权使用低温退火工艺制造器件的方法，器件和设计结构公开(公告)号：US08236709B2
公开(公告)日：2012-08-07
申请号：US12511535
申请日：2009-07-29
申请人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. Domenicucci , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： H01L21/322 , H01L21/324
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。
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3.发明申请METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE 有权使用低温退火工艺制造器件的方法，器件和设计结构公开(公告)号：US20120180010A1
公开(公告)日：2012-07-12
申请号：US13421400
申请日：2012-03-15
申请人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
发明人： Anthony G. DOMENICUCCI , Terence L. Kane , Shreesh Narasimha , Karen A. Nummy , Viorel Ontalus , Yun-Yu Wang
IPC分类号： G06F17/50
CPC分类号： H01L21/324 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.
摘要翻译： 提供了使用退火处理序列制造器件的方法。 更具体地，示出并描述了使用低温退火制造以消除位错缺陷的逻辑NFET器件，制造NFET器件的方法和设计结构。 该方法包括在栅极结构上形成应力衬垫，并对栅极结构和应力衬垫进行低温退火处理，以在栅极结构附近的单晶硅中形成堆叠力，作为记忆应力的方法。 该方法还包括从栅极结构剥离应力衬垫并在器件上在高温下进行激活退火。
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4.发明申请REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION 失效通过目标碳植入减少半导体器件中的分离形成公开(公告)号：US20120184075A1
公开(公告)日：2012-07-19
申请号：US13009020
申请日：2011-01-19
IPC分类号： H01L21/336 , H01L21/84
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。
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5.发明授权Reducing dislocation formation in semiconductor devices through targeted carbon implantation 失效通过目标碳注入减少半导体器件中的位错形成公开(公告)号：US08343825B2
公开(公告)日：2013-01-01
申请号：US13009020
申请日：2011-01-19
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26586 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.
摘要翻译： 形成半导体器件的方法包括将非晶化物质注入晶体半导体衬底中，所述衬底具有在其上形成的晶体管栅极结构。 碳被植入到基底的非晶化区域中，其特定的植入条件被定制，使得碳类的峰值浓度与堆垛层错的结束一致，其中在重结晶退火期间产生堆垛层错。 植入的碳引脚部分位错，以防止位错从堆垛层错的末端脱离，并移动到晶体管栅极结构正下方的衬底区域。 这消除了导致设备泄漏失败的缺陷。
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公开(公告)号：US20100025819A1
公开(公告)日：2010-02-04
申请号：US12185375
申请日：2008-08-04
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.
摘要翻译： 第一电极和第二电极之间的连接部分包括半导体连接部分和包括第一金属半导体合金的金属半导体合金连接部分。 电脉冲将整个连接部分转换成具有比第一金属半导体合金低的金属浓度的第二金属半导体合金。 由于第一和第二金属半导体合金之间的化学计量差异，链接部分在编程之后具有比编程之前更高的电阻。 良好控制的电阻的偏移，其有利地用作可编程精密电阻器。
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公开(公告)号：US07881093B2
公开(公告)日：2011-02-01
申请号：US12185375
申请日：2008-08-04
CPC分类号： H01L23/5256 , H01L23/5228 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.
摘要翻译： 第一电极和第二电极之间的连接部分包括半导体连接部分和包括第一金属半导体合金的金属半导体合金连接部分。 电脉冲将整个连接部分转换成具有比第一金属半导体合金低的金属浓度的第二金属半导体合金。 由于第一和第二金属半导体合金之间的化学计量差异，链接部分在编程之后具有比编程之前更高的电阻。 良好控制的电阻的偏移，其有利地用作可编程精密电阻器。
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8.发明授权Transmission electron microscopy sample preparation method for electron holography 失效透射电子显微镜用于电子全息术的样品制备方法公开(公告)号：US07214935B2
公开(公告)日：2007-05-08
申请号：US10711690
申请日：2004-09-30
申请人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
发明人： Thomas A. Bauer , Steven H. Boettcher , Anthony G. Domenicucci , John G. Gaudiello , Leon J. Kimball , Jeffrey S. McMurray , Yun-Yu Wang
CPC分类号： G01N1/32 , G01N23/04 , H01J2237/2614
摘要： A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.
摘要翻译： 制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入 。 抛光后，从样品中除去牺牲材料。
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公开(公告)号：US07102145B2
公开(公告)日：2006-09-05
申请号：US10972696
申请日：2004-10-25
IPC分类号： G01N23/04
CPC分类号： H01J37/26 , G03H5/00 , H01J37/04 , H01J2237/0492 , H01J2237/1514 , H01J2237/2614
摘要： A method for enhancing spatial resolution of a transmission electron microscopy TEM) system configured for electron holography. In an exemplary embodiment, the method includes configuring a first lens to form an initial virtual source with respect to an incident parallel beam, the initial virtual source positioned at a back focal plane of said first lens. A second lens is configured to form an intermediate virtual source with respect to the incident parallel beam, the position of said intermediate virtual source being dependent upon a focal length of the first lens and a focal length of the second lens. A third lens is configured to form a final virtual source with respect to the incident parallel beam, wherein the third lens has a focal length such that a front focal plane of the third lens lies beyond the position of the intermediate virtual source, with respect to a biprism location.
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10.发明授权Method for forming an atomically flat interface for a highly disordered metal-silicon barrier film 失效用于形成高度无序的金属 - 硅阻挡膜的原子平坦界面的方法
公开(公告)号：US6022801A
公开(公告)日：2000-02-08
申请号：US25718
申请日：1998-02-18
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/321 , H01L21/768 , H01L23/52 , H01L21/283
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/76856 , H01L21/28568 , H01L21/3212 , H01L2221/1078
摘要： A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.
摘要翻译： 公开了一种形成具有原子平坦界面的导电接触的方法。 含有钴和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。导电材料沉积在退火形成的结构的顶部。 形成了防止导电材料扩散到下面的硅衬底中的平坦界面。 该方法可以用于形成非常小的器件和浅结的接触，例如ULSI浅结所需要的。
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