公开(公告)号：US08902146B2

公开(公告)日：2014-12-02

申请号：US13943931

申请日：2013-07-17

Applicant: Samsung Display Co., Ltd.

Inventor： Beom-Jun Kim ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: G09G3/38 ,  G02F1/136 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction; a data line formed along a second direction crossing the first direction; first and second pixel electrodes spaced apart from each other; a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD的阵列基板，具有沿第一方向形成的栅极线; 沿着与第一方向交叉的第二方向形成的数据线; 第一和第二像素电极彼此间隔开; 薄膜晶体管包括连接到栅极线的栅电极; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。

公开(公告)号：US09761184B2

公开(公告)日：2017-09-12

申请号：US14173599

申请日：2014-02-05

Applicant: Samsung Display Co., Ltd.

Inventor： Hee-Joon Kim ,  Byoung-Seok Yoo ,  Jeong-Woon Lee ,  Hoi-Sik Moon

IPC: G06F1/00 ,  G09G3/36 ,  G09G3/00 ,  G09G3/20

CPC classification number: G09G3/3607 ,  G09G3/006 ,  G09G3/20 ,  G09G3/3611 ,  G09G3/3648 ,  G09G2320/0242 ,  G09G2330/10

Abstract: A method of driving a display panel includes generating corrected grayscale data utilizing a grayscale correction value of a reference pixel including m×n pixels, “m” and “n” being natural numbers greater than zero, and driving M×N pixels of the display panel based on the corrected grayscale data, “M” and “N” being natural numbers greater than zero. “M” is greater than “m” and “N” is greater than “n.”

公开(公告)号：US09406630B2

公开(公告)日：2016-08-02

申请号：US14579542

申请日：2014-12-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Joo-Han Kim ,  Ki-Yong Song ,  Dong-Ju Yang ,  Hee-Joon Kim ,  Yeo-Geon Yoon ,  Sung-Hen Cho ,  Chang-Hoon Kim ,  Jae-Hong Kim ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Ji-Young Park

IPC: H01L23/00 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L24/05 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L2224/04042 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/00

Abstract: A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

公开(公告)号：US08704748B2

公开(公告)日：2014-04-22

申请号：US13669364

申请日：2012-11-05

Applicant: Samsung Display Co., LTD.

Inventor： Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/184

Abstract: A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Abstract translation: 一种栅极驱动电路和具有该栅极驱动电路的显示装置，上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。 耦合到上拉单元的上拉驱动器从前一级之一接收进位信号，以接通上拉单元。 上拉单元接收来自下一级中的一个的门信号，将当前门信号放电至截止电压电平，并关闭上拉单元。 持有者将当前门信号保持在电压电平。 逆变器响应于第一个时钟信号打开/关闭支架。 波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极，以及耦合到反相器的输入端子的漏极，并且包括用于防止纹波施加到逆变器的纹波防止二极管 。

公开(公告)号：US20130299831A1

公开(公告)日：2013-11-14

申请号：US13943931

申请日：2013-07-17

Applicant: Samsung Display Co., Ltd.

Inventor： BEOM-JUN KIM ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction;a data line formed along a second direction crossing the first direction;first and second pixel electrodes spaced apart from each other;a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD阵列基板，具有：沿着第一方向形成的栅极线;沿着与第一方向交叉的第二方向形成的数据线;第一和第二像素电极，彼此间​​隔开;薄膜晶体管，包括栅电极 连接到门线; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。