公开(公告)号：US09824661B2

公开(公告)日：2017-11-21

申请号：US15195263

申请日：2016-06-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung-Man Kim ,  Hong-Woo Lee ,  Jong-Hwan Lee ,  Hyeon-Hwan Kim ,  Jong-Hyuk Lee

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2300/0443 ,  G09G2300/0465 ,  G09G2300/0809 ,  G09G2310/0202 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/0666

Abstract: A display apparatus includes: a plurality of pixel blocks, each pixel block of the plurality of pixel blocks including a first pixel electrode connected to a first switching element and a second pixel electrode connected to a second switching element; gate lines which extend along a first direction and include a first gate line connected to the first switching element and a second gate line connected to the second switching element; and data lines which extend along a second direction intersecting the first direction. A gate voltage is applied to the first gate line before the second gate line, and the first pixel electrode of each of the pixel blocks displays a same color.

公开(公告)号：US08902146B2

公开(公告)日：2014-12-02

申请号：US13943931

申请日：2013-07-17

Applicant: Samsung Display Co., Ltd.

Inventor： Beom-Jun Kim ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: G09G3/38 ,  G02F1/136 ,  G02F1/1343 ,  H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction; a data line formed along a second direction crossing the first direction; first and second pixel electrodes spaced apart from each other; a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD的阵列基板，具有沿第一方向形成的栅极线; 沿着与第一方向交叉的第二方向形成的数据线; 第一和第二像素电极彼此间隔开; 薄膜晶体管包括连接到栅极线的栅电极; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。

公开(公告)号：US08704748B2

公开(公告)日：2014-04-22

申请号：US13669364

申请日：2012-11-05

Applicant: Samsung Display Co., LTD.

Inventor： Sung-Man Kim ,  Hong-Woo Lee ,  Myung-Koo Hur ,  Hee-Joon Kim

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0286 ,  G11C19/184

Abstract: A gate driving circuit and a display device having the same, a pull-up unit pulls up a current gate signal by using a first clock signal during a first period of one frame. A pull-up driver coupled to the pull-up unit receives a carry signal from one of the previous stages to turn on the pull-up unit. A pull-up unit receives a gate signal from one of the next stages, discharges the current gate signal to an off voltage level, and turns off the pull-up unit. A holder holds the current gate signal at the voltage level. An inverter turns on/off the holder in response to a first clock signal. A ripple preventer has a source and a gate coupled in common to an output terminal of the pull-up unit and a drain coupled to an input terminal of the inverter, and includes a ripple preventing diode for preventing a ripple from being applied to the inverter.

Abstract translation: 一种栅极驱动电路和具有该栅极驱动电路的显示装置，上拉单元在一帧的第一周期期间通过使用第一时钟信号来上拉电流门信号。 耦合到上拉单元的上拉驱动器从前一级之一接收进位信号，以接通上拉单元。 上拉单元接收来自下一级中的一个的门信号，将当前门信号放电至截止电压电平，并关闭上拉单元。 持有者将当前门信号保持在电压电平。 逆变器响应于第一个时钟信号打开/关闭支架。 波纹防止器具有与上拉单元的输出端子共同耦合的源极和栅极，以及耦合到反相器的输入端子的漏极，并且包括用于防止纹波施加到逆变器的纹波防止二极管 。

公开(公告)号：US10777159B2

公开(公告)日：2020-09-15

申请号：US15805754

申请日：2017-11-07

Applicant: Samsung Display Co., Ltd.

Inventor： Noboru Takeuchi ,  Masami Igawa ,  Min soo Kang ,  Beomjun Kim ,  YoonHo Kim ,  Seongyeol Syn ,  Hong-Woo Lee

IPC: G09G3/36 ,  G11C19/28

Abstract: Each stage of a gate driver includes a controlling part which increases an electric potential of a boosting line in response to a carry signal of a previous stage and decreases the electric potential of the boosting line in response to the carry signal of a next stage, a first output part which turns on in response to the increased electric potential of the boosting line and receiving a clock signal to output a gate signal of a present stage, and a second output part which turns on in response to the increased electric potential of the boosting line and receiving the clock signal to output the carry signal of the present stage. The boosting line of the present stage is disposed adjacent to a gate line which is connected to one of next stages following the present stage.

公开(公告)号：US20130299831A1

公开(公告)日：2013-11-14

申请号：US13943931

申请日：2013-07-17

Applicant: Samsung Display Co., Ltd.

Inventor： BEOM-JUN KIM ,  Hee-Joon Kim ,  Hong-Woo Lee ,  Hye-Rhee Han ,  Hyeong-Jun Park ,  Jin-Suk Seo

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286

Abstract: An array substrate of an LCD having: a gate line formed along a first direction;a data line formed along a second direction crossing the first direction;first and second pixel electrodes spaced apart from each other;a thin-film transistor includes a gate electrode connected to the gate line; a source electrode connected to the data line and partially overlapping the second pixel electrode; and a drain electrode connected to the first pixel electrode spaced apart from the second pixel electrode along the second direction. The source electrode or the gate electrode overlaps the second pixel electrode but the drain electrode does not overlap the second pixel electrode. Electrical coupling between the first and second pixel electrodes are avoided with such configuration.

Abstract translation: 一种LCD阵列基板，具有：沿着第一方向形成的栅极线;沿着与第一方向交叉的第二方向形成的数据线;第一和第二像素电极，彼此间​​隔开;薄膜晶体管，包括栅电极 连接到门线; 源极连接到数据线并部分地与第二像素电极重叠; 以及漏极，其沿着所述第二方向连接到与所述第二像素电极间隔开的所述第一像素电极。 源电极或栅电极与第二像素电极重叠，但漏电极不与第二像素电极重叠。 通过这种配置可以避免第一和第二像素电极之间的电耦合。

公开(公告)号：US20160204136A1

公开(公告)日：2016-07-14

申请号：US14968634

申请日：2015-12-14

Applicant: SAMSUNG DISPLAY CO., LTD

Inventor： Noboru TAKEUCHI ,  Min-Soo KANG ,  Beom-Jun Kim ,  Yoon-Ho Kim ,  Seong-Yeol SYN ,  Hong-Woo Lee

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/31 ,  H01L29/49 ,  G09G3/36 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1343 ,  G06F1/04 ,  H01L29/24 ,  G02F1/1368

CPC classification number: H01L29/4966 ,  G09G3/3611 ,  G09G3/3674 ,  G09G3/3696 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28 ,  H01L23/3171 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/495 ,  H01L29/78648 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor and a liquid crystal display device having the same are provided. The transistor includes a first gate electrode disposed on a base substrate; a gate insulating layer disposed on the first gate electrode; a semiconductor layer disposed on the gate insulating layer, and including a channel area; a source electrode and a drain electrode connected to both ends of the semiconductor layer; a passivation layer configured to cover the semiconductor layer, the source electrode, and the drain electrode; and a second gate electrode disposed on the passivation layer, and partially overlapping the channel area in a direction from the drain electrode toward the source electrode.

Abstract translation: 提供了具有该晶体管和液晶显示装置的晶体管。 晶体管包括设置在基底基板上的第一栅电极; 设置在所述第一栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体层，并且包括沟道区域; 源电极和漏电极，连接到半导体层的两端; 被配置为覆盖所述半导体层，所述源电极和所述漏电极的钝化层; 以及设置在所述钝化层上的第二栅极电极，并且在从所述漏极电极朝向所述源极电极的方向上部分地与所述沟道区域重叠。