Thin film transistor
    2.
    发明授权
    Thin film transistor 有权
    薄膜晶体管

    公开(公告)号:US09508856B2

    公开(公告)日:2016-11-29

    申请号:US14436241

    申请日:2013-10-15

    CPC classification number: H01L29/78606 H01L29/7869 H01L29/78693

    Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

    Abstract translation: 提供一种薄膜晶体管,其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制,并且实现了稳定的特性。 该薄膜晶体管的特征在于:薄膜晶体管具有由至少含有In,Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。

    Display device and method of fabricating the same

    公开(公告)号:US11942488B2

    公开(公告)日:2024-03-26

    申请号:US18193200

    申请日:2023-03-30

    CPC classification number: H01L27/124 H01L27/1262 H10K59/131

    Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.

    Display device and method of fabricating the same

    公开(公告)号:US11894355B2

    公开(公告)日:2024-02-06

    申请号:US17471581

    申请日:2021-09-10

    CPC classification number: H01L25/167 H01L27/124 H01L27/1259

    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.

    Display device and method for fabricating the same

    公开(公告)号:US11765947B2

    公开(公告)日:2023-09-19

    申请号:US17107638

    申请日:2020-11-30

    CPC classification number: H10K59/131 H10K59/122 H10K59/1201

    Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

    Display device and manufacturing method thereof

    公开(公告)号:US12218151B2

    公开(公告)日:2025-02-04

    申请号:US18480494

    申请日:2023-10-03

    Abstract: A display device according to an embodiment of the present disclosure includes: a substrate; a first conductive layer on the substrate; a first insulating layer on the first conductive layer; an active pattern on the first insulating layer and including a semiconductor material; a second insulating layer on the active pattern; and a second conductive layer on the second insulating layer, wherein the first insulating layer has a first opening exposing the first conductive layer, the second insulating layer has a second opening exposing the first conductive layer, a breadth of the first opening is different than a breadth of the second opening, and a side surface of the first opening and a side surface of the second opening are formed to a top surface of the first conductive layer.

    Display device and method of fabricating the same

    公开(公告)号:US11626426B2

    公开(公告)日:2023-04-11

    申请号:US17109601

    申请日:2020-12-02

    Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.

    Display device and method of manufacturing the same

    公开(公告)号:US11594559B2

    公开(公告)日:2023-02-28

    申请号:US17157184

    申请日:2021-01-25

    Abstract: A display device may include a first gate electrode disposed on a substrate, a buffer layer disposed on the first gate electrode, a first active pattern on the buffer layer, the first active pattern overlapping the first gate electrode and including an oxide semiconductor, a second active pattern on the buffer layer, spaced apart from the first active pattern, and including an oxide semiconductor, the second active pattern including a channel region, and a source region and a drain region, a source pattern and a drain pattern respectively at ends of the first active pattern, a first insulation pattern disposed on the first active pattern, a second insulation pattern disposed on the channel region, a first oxygen supply pattern on the first insulation pattern, a second oxygen supply pattern on the second insulation pattern, and a second gate electrode on the second oxygen supply pattern.

    THIN FILM TRANSISTOR
    10.
    发明申请
    THIN FILM TRANSISTOR 有权
    薄膜晶体管

    公开(公告)号:US20150249159A1

    公开(公告)日:2015-09-03

    申请号:US14436241

    申请日:2013-10-15

    CPC classification number: H01L29/78606 H01L29/7869 H01L29/78693

    Abstract: Provided is a thin film transistor wherein the shape of a protrusion formed on the interface between an oxide semiconductor layer and a protection film is suitably controlled, and stable characteristics are achieved. This thin film transistor is characterized in that: the thin film transistor has an oxide semiconductor layer formed of an oxide containing at least In, Zn and Sn as metal elements, and a protection film directly in contact with the oxide semiconductor layer; and the maximum height of a protrusion formed on the oxide semiconductor layer surface directly in contact with the protection film is less than 5 nm.

    Abstract translation: 提供一种薄膜晶体管,其中形成在氧化物半导体层和保护膜之间的界面上的突起的形状被适当地控制,并且实现了稳定的特性。 该薄膜晶体管的特征在于:薄膜晶体管具有由至少含有In,Zn和Sn作为金属元素的氧化物和与氧化物半导体层直接接触的保护膜形成的氧化物半导体层; 在与保护膜直接接触的氧化物半导体层表面上形成的突起的最大高度小于5nm。

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