Display device
    3.
    发明授权

    公开(公告)号:US11501711B2

    公开(公告)日:2022-11-15

    申请号:US16906688

    申请日:2020-06-19

    Abstract: A display device includes: a (k−1)-th scan line and a k-th scan line which are parallel to each other; a j-th data line which crosses the (k−1)-th scan line and the k-th scan line; and a subpixel connected to the (k−1)-th scan line, the k-th scan line, and the j-th data line, wherein the subpixel includes: a driving transistor configured to control a driving current flowing from a first electrode thereof to a second electrode thereof according to a data voltage applied to a first gate electrode thereof, the driving transistor having a second gate electrode connected to the (k−1)-th scan line; and a light emitting element configured to emit light according to the driving current.

    Thin film transistor array panel and manufacturing method thereof

    公开(公告)号:US10217767B2

    公开(公告)日:2019-02-26

    申请号:US15434150

    申请日:2017-02-16

    Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

    Thin film transistor array panel and manufacturing method thereof

    公开(公告)号:US10748936B2

    公开(公告)日:2020-08-18

    申请号:US16232244

    申请日:2018-12-26

    Abstract: A thin film transistor array panel includes a substrate and a thin film transistor disposed on a surface of the substrate. The thin film transistor includes a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another. The semiconductor is between the source electrode and the drain electrode. The thin film transistor array panel further includes a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material. The first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode.

    ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE
    8.
    发明申请

    公开(公告)号:US20200005708A1

    公开(公告)日:2020-01-02

    申请号:US16356142

    申请日:2019-03-18

    Abstract: An organic light emitting diode display includes a driving transistor and a compensation transistor. The driving transistor includes a first gate electrode disposed on a substrate, a polycrystalline semiconductor layer disposed on the first gate electrode of the driving transistor and including a first electrode, a second electrode, and a channel, and a second gate electrode disposed on the polycrystalline semiconductor layer of the driving transistor. The compensation transistor includes a polycrystalline semiconductor layer including a first electrode, a second electrode, and a channel, and a gate electrode disposed on the polycrystalline semiconductor layer of the compensation transistor.

    PIXEL AND DISPLAY DEVICE USING THE SAME
    9.
    发明申请

    公开(公告)号:US20190279567A1

    公开(公告)日:2019-09-12

    申请号:US16285080

    申请日:2019-02-25

    Abstract: A pixel includes: an organic light emitting diode; a first transistor including a gate that is connected to a first node, wherein the first transistor is connected between a second node and a third node; a second transistor including a gate that is connected to a corresponding scan line, wherein the second transistor is connected between a data line and the second node; a storage capacitor connected between the first node and a first voltage; a third transistor including a gate that is connected to the corresponding scan line, the third transistor is connected between the first node and the third node; and a fourth transistor connected between a first end of the first transistor and a second voltage.

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