公开(公告)号：US09502536B2

公开(公告)日：2016-11-22

申请号：US14795578

申请日：2015-07-09

Applicant: Samsung Display Co., Ltd.

Inventor： Dong Il Kim ,  Joo Hyung Lee ,  Jae Woo Jeong

IPC: H01L21/467 ,  H01L21/786 ,  H01L29/66 ,  H01L27/12 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L29/66765 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/127 ,  H01L27/1288

Abstract: Provided is a manufacturing method of a thin film transistor array panel including: formation of a gate line including a gate electrode on a substrate; formation of sequentially a gate insulating layer, an active layer, a data metal layer, and a photoresist etching mask pattern on the gate line; etching the data metal layer with the same shape as the photoresist etching mask pattern; etching the active layer by using the photoresist etching mask pattern; formation of a data line including a source electrode and a drain electrode for completing a channel region on the active layer; and formation of a pixel electrode exposing the drain electrode and electrically connected with the drain electrode, in which in the etching of the active layer, a dry-etch process is performed by using gas including at least one of NF3 and H2.

Abstract translation: 提供一种薄膜晶体管阵列面板的制造方法，包括：在基板上形成包括栅电极的栅极线; 在栅极线上依次形成栅极绝缘层，有源层，数据金属层和光致抗蚀剂蚀刻掩模图案; 以与光致抗蚀剂蚀刻掩模图案相同的形状蚀刻数据金属层; 通过使用光致抗蚀剂蚀刻掩模图案蚀刻有源层; 形成包括用于完成有源层上的沟道区的源电极和漏电极的数据线; 以及形成暴露漏电极并与漏电极电连接的像素电极，其中在有源层的蚀刻中，通过使用包括NF 3和H 2中的至少一个的气体进行干蚀刻工艺。

公开(公告)号：US09153603B2

公开(公告)日：2015-10-06

申请号：US14105048

申请日：2013-12-12

Applicant: Samsung Display Co., Ltd.

Inventor： Ji-Young Park ,  Dong Il Kim ,  Sang Gab Kim

IPC: H01L21/00 ,  H01L27/12

CPC classification number: H01L27/124 ,  G02F1/134363 ,  G02F1/136227 ,  H01L27/1248 ,  H01L27/1259

Abstract: A thin film transistor array panel includes a substrate; a gate line located over the substrate and including a gate pad portion; a data line located over the gate line and including a source electrode and a data pad portion; a drain electrode; a first passivation layer located over the data line and the drain electrode; an organic insulating layer located over the first passivation layer and having a contact hole; a first field generating electrode located over the organic insulating layer and having an opening; a second passivation layer located over the first field generating electrode; and a second field generating electrode located over the second passivation layer. The contact hole coincides with or is smaller than the opening, and the contact hole has a tapered structure.

Abstract translation: 薄膜晶体管阵列面板包括基板; 栅极线，位于衬底上并包括栅极焊盘部分; 位于栅极线上方并包括源电极和数据焊盘部分的数据线; 漏电极; 位于数据线和漏电极之上的第一钝化层; 位于所述第一钝化层上并具有接触孔的有机绝缘层; 位于所述有机绝缘层上方并具有开口的第一场产生电极; 位于第一场产生电极之上的第二钝化层; 以及位于第二钝化层上方的第二场产生电极。 接触孔与开口重合或小于开口，接触孔具有锥形结构。

公开(公告)号：US08940565B1

公开(公告)日：2015-01-27

申请号：US14194015

申请日：2014-02-28

Applicant: Samsung Display Co. Ltd.

Inventor： Ji Young Park ,  Gwan Ha Kim ,  Dong Il Kim ,  Sang Gab Kim

IPC: H01L21/00 ,  H01L27/12

CPC classification number: H01L27/1259 ,  G02F2001/134372

Abstract: A method of manufacturing a thin film transistor array substrate includes providing a plurality of gate lines and a plurality of data lines on a first substrate, providing an organic layer on the gate lines and the data lines, providing a first electrode on the organic layer, providing a passivation layer on the first electrode, providing a second electrode on the passivation layer, providing a first cover layer on the second electrode to cover the second electrode, providing a plurality of photosensitive layer patterns on the first cover layer, providing a plurality of first cutout patterns in the first cover layer and a plurality of second cutout patterns in the second electrode using the photosensitive layer patterns as an etch mask, and providing a plurality of third cutout patterns in the passivation layer using the first cover layer as an etch mask.

Abstract translation: 制造薄膜晶体管阵列基板的方法包括：在第一基板上设置多个栅极线和多个数据线，在栅极线和数据线上提供有机层，在有机层上提供第一电极， 在所述第一电极上提供钝化层，在所述钝化层上提供第二电极，在所述第二电极上提供第一覆盖层以覆盖所述第二电极，在所述第一覆盖层上提供多个感光层图案，提供多个 第一覆盖层中的第一切除图案和使用感光层图案作为蚀刻掩模的第二电极中的多个第二切割图案，并且使用第一覆盖层作为蚀刻掩模在钝化层中提供多个第三切除图案 。

公开(公告)号：US10423042B2

公开(公告)日：2019-09-24

申请号：US15228549

申请日：2016-08-04

Applicant: Samsung Display Co. Ltd.

Inventor： Joo Hyung Lee ,  Shin Il Choi ,  Kyeong Su Ko ,  Dong Il Kim ,  Jong Mo Yeo

IPC: G02F1/1368 ,  H01L29/417 ,  H01L21/3213 ,  H01L27/12

Abstract: A liquid crystal display device includes a substrate; a gate electrode on the substrate; a semiconductor pattern layer on the gate electrode; and source and drain electrodes on the semiconductor pattern layer and spaced apart from each other. The source electrode includes: a first facing portion facing the drain electrode; and a first protrusion protruding toward the drain electrode from the first protrusion. The drain electrode includes: a second facing portion facing the source electrode; and a second protrusion protruding toward the source electrode from the second facing portion and facing the first protrusion. The semiconductor pattern layer includes: a source area overlapping the source electrode; a drain area overlapping the drain electrode; and a bridge area connecting the source area with the drain area, and a space defined between the first protrusion and the second protrusion is on the bridge area.

公开(公告)号：US09711545B2

公开(公告)日：2017-07-18

申请号：US15262943

申请日：2016-09-12

Applicant: Samsung Display Co. Ltd.

Inventor： Ji Young Park ,  Dong Il Kim ,  Sang Gab Kim

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/1288 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L27/124

Abstract: A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer.