-
公开(公告)号：US09508857B2
公开(公告)日：2016-11-29
申请号：US14635732
申请日：2015-03-02
Inventor： Byung Du Ahn , Ji Hun Lim , Jun Hyung Lim , Dae Hwan Kim , Jae Hyeong Kim , Je Hun Lee , Hyun Kwang Jung
IPC: H01L29/786 , H01L27/12 , H01L21/28
CPC classification number: H01L29/78606 , H01L21/28 , H01L27/124 , H01L29/786 , H01L29/78678 , H01L29/7869 , H01L29/78696
Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
-
公开(公告)号：US09257563B2
公开(公告)日：2016-02-09
申请号：US13798811
申请日：2013-03-13
Inventor： Byung Du Ahn , Jung Hwa Kim , Ji Hun Lim , Je Hun Lee , Dae Hwan Kim , Hyun Kwang Jung
IPC: H01L29/10 , H01L29/786 , H01L29/66 , H01L33/38 , H01L29/417
CPC classification number: H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78693 , H01L33/387
Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.
Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。
-
公开(公告)号：US08969872B2
公开(公告)日：2015-03-03
申请号：US13789335
申请日：2013-03-07
Applicant: Samsung Display Co., Ltd.
Inventor： Byung Du Ahn , Ji Hun Lim , Jun Hyung Lim , Dae Hwan Kim , Jae Hyeong Kim , Je Hun Lee , Hyun Kwang Jung
IPC: H01L29/04 , H01L29/786 , H01L21/28
CPC classification number: H01L29/78606 , H01L21/28 , H01L27/124 , H01L29/786 , H01L29/78678 , H01L29/7869 , H01L29/78696
Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。
-
-
Search Results
3
records
(took 0.014 seconds)
