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    Thin film transistor and manufacturing method thereof
    1.
    发明授权
    Thin film transistor and manufacturing method thereof 有权
    薄膜晶体管及其制造方法

    公开(公告)号：US09142682B2

    公开(公告)日：2015-09-22

    申请号：US13826905

    申请日：2013-03-14

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Ji Hun Lim ,  Jun Ho Song

    IPC分类号： H01L29/786 ,  H01L29/66

    CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

    摘要： A thin film transistor and a manufacturing method thereof. The thin film transistor includes: a gate electrode; a gate insulating layer disposed on the gate electrode; a first semiconductor disposed on the gate insulating layer; a second semiconductor disposed on the first semiconductor and having a different plane shape from the first semiconductor; and a source electrode and a drain electrode that are disposed on the second semiconductor and face each other.

    摘要翻译： 一种薄膜晶体管及其制造方法。 薄膜晶体管包括：栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的第一半导体; 设置在所述第一半导体上并且具有与所述第一半导体不同的平面形状的第二半导体; 以及设置在第二半导体上并且彼此面对的源电极和漏电极。

    Thin film transistor array panel
    3.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号：US09455333B2

    公开(公告)日：2016-09-27

    申请号：US14809830

    申请日：2015-07-27

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L29/40 ,  H01L21/28 ,  H01L21/268 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  H01L29/86

    CPC分类号： H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

    摘要： A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.

    摘要翻译： 薄膜晶体管阵列面板包括衬底，设置在衬底上的遮光膜，覆盖遮光膜的缓冲层和设置在缓冲层上的沟道区。 源极区域和漏极区域设置在与沟道区域相同的层中。 栅极绝缘层设置在沟道区上，并且栅电极与沟道区重叠，栅极绝缘层介于栅电极和沟道区之间。 钝化层设置在栅电极，源极区，漏极区和缓冲层上。 源电极和漏极设置在钝化层上，其中沟道区，源区和漏区包括氧化物半导体，并且其中源极区和漏极区的载流子浓度大于 渠道区域。

    Thin film transistor array panel including layered line structure and method for manufacturing the same
    4.
    发明授权
    Thin film transistor array panel including layered line structure and method for manufacturing the same 有权
    薄膜晶体管阵列面板包括分层线结构及其制造方法

    公开(公告)号：US08637869B2

    公开(公告)日：2014-01-28

    申请号：US13669278

    申请日：2012-11-05

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Yang Ho Bae ,  Beom-Seok Cho ,  Chang Oh Jeong

    IPC分类号： H01L29/04

    CPC分类号： H01L27/1214 ,  H01L27/1225 ,  H01L27/124

    摘要： The present invention provides a thin film transistor array panel comprising an insulating substrate; a gate line formed on the insulating substrate; a gate insulating layer formed on the gate line; a drain electrode and a data line having a source electrode formed on the gate insulating layer, the drain electrode being adjacent to the source electrode with a gap therebetween; and a pixel electrode coupled to the drain electrode, wherein at least one of the gate line, the data line, and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper (Cu).

    摘要翻译： 本发明提供一种薄膜晶体管阵列板，其包括绝缘基板; 形成在所述绝缘基板上的栅极线; 栅极绝缘层，形成在栅极线上; 漏电极和数据线，其具有形成在所述栅极绝缘层上的源电极，所述漏电极与所述源电极相邻，其间具有间隙; 以及耦合到所述漏电极的像素电极，其中所述栅极线，所述数据线和所述漏电极中的至少一个包括包括导电氧化物的第一导电层和包含铜（Cu）的第二导电层。

    Oxide semicondutor thin film transistor
    10.
    发明授权
    Oxide semicondutor thin film transistor 有权
    氧化物半导体薄膜晶体管

    公开(公告)号：US09093540B2

    公开(公告)日：2015-07-28

    申请号：US13683468

    申请日：2012-11-21

    申请人： Samsung Display Co., Ltd.

    发明人： Je Hun Lee ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

    IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L29/86

    CPC分类号： H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

    摘要： The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region include an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.

    摘要翻译： 本发明涉及薄膜晶体管，薄膜晶体管阵列面板及其制造方法。 根据本发明的示例性实施例的薄膜晶体管包括：栅电极; 位于栅极电极上或下方的栅极绝缘层; 与所述栅电极重叠的沟道区，位于所述沟道区与所述栅电极之间的所述栅绝缘层; 以及源极区域和漏极区域，其相对于沟道区域彼此面对，位于与沟道区域相同的层中，并且连接到沟道区域，其中沟道区域，源极区域和漏极区域包括 氧化物半导体，其中源极区域和漏极区域的载流子浓度大于沟道区域的载流子浓度。