公开(公告)号：US20190355752A1

公开(公告)日：2019-11-21

申请号：US16438385

申请日：2019-06-11

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12

Abstract: A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20150311230A1

公开(公告)日：2015-10-29

申请号：US14793183

申请日：2015-07-07

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.

Abstract translation: 制造薄膜晶体管（TFT）阵列基板的方法包括在基板上形成栅极线和栅电极，在栅极线和栅电极上形成栅极绝缘层和氧化物半导体层，形成蚀刻停止图案 在薄膜晶体管区域和栅极线和数据线彼此重叠的区域中，在氧化物半导体层和蚀刻停止图案上形成数据导体，数据导体包括源电极和漏极，构成 TFT与栅极电极一起形成，并且在与栅极线相交的方向上形成数据线。

公开(公告)号：US20170077144A1

公开(公告)日：2017-03-16

申请号：US15342756

申请日：2016-11-03

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.

Abstract translation: 一种基板，包括栅极布线和设置在基板上的栅极电极的栅极布线，设置在与栅极布线相同的层上的存储线，设置在栅极布线和存储线上的栅极绝缘层，设置的氧化物半导体层图案 在栅极绝缘层上，包括与栅极线交叉的数据线的数据布线，设置在氧化物半导体层图案的一侧上的源电极和设置在氧化物半导体层的另一侧上的漏极，以及包括 设置在所述存储线和所述数据线之间并且部分地重叠所述数据线和所述存储线的第一蚀刻停止部。

公开(公告)号：US20230178659A1

公开(公告)日：2023-06-08

申请号：US17875336

申请日：2022-07-27

Applicant: Samsung Display Co., LTD.

Inventor： Hyun-Jung LEE

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/7869 ,  H01L29/66742

Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof, and the thin film transistor according to an embodiment includes: a substrate; a buffer layer positioned on the substrate and defining a trench on an upper surface thereof; a semiconductor positioned in the trench of the buffer layer; a gate electrode overlapping the semiconductor in a plan view; and a source electrode and a drain electrode, which are connected to the semiconductor.

公开(公告)号：US20220384491A1

公开(公告)日：2022-12-01

申请号：US17886489

申请日：2022-08-12

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

公开(公告)号：US20180083040A1

公开(公告)日：2018-03-22

申请号：US15813758

申请日：2017-11-15

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A substrate including gate wirings including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate wirings and the oxide semiconductor layer pattern, data wirings including a data line crossing the gate line, a source electrode connected to one side of the oxide semiconductor layer pattern, and a drain electrode connected to another side of the oxide semiconductor layer, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20210143187A1

公开(公告)日：2021-05-13

申请号：US17124497

申请日：2020-12-17

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US20160020331A1

公开(公告)日：2016-01-21

申请号：US14858281

申请日：2015-09-18

Applicant: Samsung Display Co., Ltd.

Inventor： Ki-Won KIM ,  Kap-Soo YOON ,  Do-Hyun KIM ,  Hyun-Jung LEE

IPC: H01L29/786 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/66765 ,  H01L29/78633

Abstract: A display substrate is provided. The display substrate includes a gate interconnection disposed on an insulating substrate, an oxide semiconductor pattern disposed on the gate interconnection and including an oxide semiconductor, and a data interconnection disposed on the oxide semiconductor pattern to interconnect the gate interconnection. The oxide semiconductor pattern includes a first oxide semiconductor pattern having a first oxide and a first element and a second oxide semiconductor pattern having a second oxide.

Abstract translation: 提供显示基板。 显示基板包括布置在绝缘基板上的栅极互连，设置在栅极互连上并包括氧化物半导体的氧化物半导体图案，以及布置在氧化物半导体图案上以互连栅极互连的数据互连。 氧化物半导体图案包括具有第一氧化物和第一元素的第一氧化物半导体图案以及具有第二氧化物的第二氧化物半导体图案。