Abstract:
A substrate including gate wirings including gate line and a gate electrode disposed on the substrate, a storage line disposed on the same layer as the gate wirings, a gate insulating layer disposed on the gate wirings and the storage line, an oxide semiconductor layer pattern disposed on the gate insulating layer, data wirings including a data line crossing the gate line, a source electrode disposed on one side of the oxide semiconductor layer pattern, and a drain electrode disposed on another side of the oxide semiconductor layer, and an etch stopper including a first etch stopper portion disposed between the storage line and the data line and partially overlapping both the data line and the storage line.
Abstract:
A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
Abstract:
A display panel includes first to third test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer, and disposed adjacent to the first test pad in the second direction, a third test pad electrically connected to the third test line and disposed adjacent to the first test pad in the first direction, the third test pad and the third test line being formed from a same layer.
Abstract:
A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.
Abstract:
A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, and a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer and disposed adjacent to the first test pad in the second direction.
Abstract:
A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.
Abstract:
A substrate including a gate line and a gate electrode disposed on a substrate, an oxide semiconductor layer pattern overlapping the gate electrode, a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a source electrode electrically connected to the oxide semiconductor layer pattern, a drain electrode electrically connected to the oxide semiconductor layer, the drain electrode spaced apart from the source electrode, and an insulating pattern including a first portion, which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.
Abstract:
A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.
Abstract:
A method of manufacturing a thin film transistor (TFT) array substrate includes forming a gate line and a gate electrode on a substrate, forming a gate-insulating layer and an oxide semiconductor layer on the gate line and the gate electrode, forming etch stop patterns at a thin-film transistor area and an area where the gate line and the data line overlap each other, forming a data conductor on the oxide semiconductor layer and the etch stop patterns, the data conductor comprising a source electrode and a drain electrode that constitute a TFT together with the gate electrode, and forming a data line extending in a direction intersecting the gate line.
Abstract:
A method of fabricating a thin-film transistor substrate includes disposing an oxide semiconductor layer on an insulating substrate, performing a thermal treatment process to the oxide semiconductor layer, providing an alignment mark, a source electrode, a drain electrode, and an oxide semiconductor pattern, after the thermal treatment process, providing a gate electrode, after the thermal treatment process, and providing a pixel electrode connected to the drain electrode.