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公开(公告)号：US11436477B2
公开(公告)日：2022-09-06
申请号：US16857740
申请日：2020-04-24
发明人： Yuhwan Ro , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号：US11600340B2
公开(公告)日：2023-03-07
申请号：US17462298
申请日：2021-08-31
发明人： Seungwoo Seo , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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公开(公告)号：US11886985B2
公开(公告)日：2024-01-30
申请号：US17876136
申请日：2022-07-28
发明人： Yuhwan Ro , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
CPC分类号： G06N3/063 , G06F9/3001 , G06F9/30145 , G06F9/3802 , G06F17/16 , G06N3/082 , G06N20/10
摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.
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公开(公告)号：US11139033B2
公开(公告)日：2021-10-05
申请号：US16833864
申请日：2020-03-30
发明人： Seungwoo Seo , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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公开(公告)号：US11037618B2
公开(公告)日：2021-06-15
申请号：US16858468
申请日：2020-04-24
发明人： Eojin Lee , Ingab Kang , Jung Ho Ahn
IPC分类号： G11C11/406 , G11C11/4076 , G11C11/409 , G11C11/408 , G11C11/4072
摘要： A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.
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公开(公告)号：US11568917B1
公开(公告)日：2023-01-31
申请号：US17504705
申请日：2021-10-19
发明人： Hoon Shin , Yeonhong Park , Jaewook Lee , Eojin Lee , Woosuk Kwon , Jungho Ahn , Taejun Ham
IPC分类号： G11C11/4078
摘要： A hammer refresh row address detector includes a control logic unit that receives a row address applied along with an active command, to increase a hit count stored in a corresponding entry when the row address is present in candidate aggressor row addresses stored in n entries. The control logic determines a candidate aggressor row address stored in an entry in which the hit count equals a threshold value to be a target aggressor row address. The control logic generates a victim row address adjacent to the target aggressor row address as a hammer refresh row address to accompany a hammer refresh command. The control logic increases the miss count value when the row address is not present in the candidate aggressor row addresses stored in the n entries and no hit count within the n entries is identical to the miss count value.
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公开(公告)号：US20240365528A1
公开(公告)日：2024-10-31
申请号：US18643224
申请日：2024-04-23
发明人： Changhoon SUNG , Hyojin Cho , Hoyoung Tang , Taehyung Kim , Eojin Lee
IPC分类号： H10B10/00 , G11C5/06 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H10B10/125 , G11C5/063 , H01L23/5283 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.
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