公开(公告)号：US11886985B2

公开(公告)日：2024-01-30

申请号：US17876136

申请日：2022-07-28

申请人： Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

发明人： Yuhwan Ro ,  Byeongho Kim ,  Jaehyun Park ,  Jungho Ahn ,  Minbok Wi ,  Sunjung Lee ,  Eojin Lee ,  Wonkyung Jung ,  Jongwook Chung ,  Jaewan Choi

IPC分类号： G06N3/063 ,  G06N3/082 ,  G06N20/10 ,  G06F17/16 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06N3/063 ,  G06F9/3001 ,  G06F9/30145 ,  G06F9/3802 ,  G06F17/16 ,  G06N3/082 ,  G06N20/10

摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US11139033B2

公开(公告)日：2021-10-05

申请号：US16833864

申请日：2020-03-30

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Seungwoo Seo ,  Byeongho Kim ,  Jaehyun Park ,  Jungho Ahn ,  Minbok Wi ,  Sunjung Lee ,  Eojin Lee ,  Wonkyung Jung ,  Jongwook Chung ,  Jaewan Choi

IPC分类号： G11C16/04 ,  G11C16/30 ,  G06N3/02 ,  G11C5/02 ,  G11C16/10

摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

公开(公告)号：US11436477B2

公开(公告)日：2022-09-06

申请号：US16857740

申请日：2020-04-24

申请人： Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

发明人： Yuhwan Ro ,  Byeongho Kim ,  Jaehyun Park ,  Jungho Ahn ,  Minbok Wi ,  Sunjung Lee ,  Eojin Lee ,  Wonkyung Jung ,  Jongwook Chung ,  Jaewan Choi

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F17/16 ,  G06F9/38 ,  G06F9/30

摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US11600340B2

公开(公告)日：2023-03-07

申请号：US17462298

申请日：2021-08-31

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Seungwoo Seo ,  Byeongho Kim ,  Jaehyun Park ,  Jungho Ahn ,  Minbok Wi ,  Sunjung Lee ,  Eojin Lee ,  Wonkyung Jung ,  Jongwook Chung ,  Jaewan Choi

IPC分类号： G11C16/30 ,  G06N3/02 ,  G11C5/02 ,  G11C16/10

摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

公开(公告)号：US20240330171A1

公开(公告)日：2024-10-03

申请号：US18515565

申请日：2023-11-21

申请人： Samsung Electronics Co., Ltd.

发明人： Jaeyoung Heo ,  Byeongho Kim ,  Yuhwan Ro ,  Sungjoo Yoo ,  Suk Han Lee

IPC分类号： G06F12/02

CPC分类号： G06F12/023

摘要： Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

公开(公告)号：US20240161850A1

公开(公告)日：2024-05-16

申请号：US18362130

申请日：2023-07-31

申请人： Samsung Electronics Co., Ltd.

发明人： Byeongho Kim ,  Shinhaeng Kang ,  Suk Han Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC分类号： G11C29/18 ,  G11C29/12

CPC分类号： G11C29/18 ,  G11C29/1201 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.