公开(公告)号：US20240363625A1

公开(公告)日：2024-10-31

申请号：US18422471

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Young Gwon Kim ,  Soo Jin Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor includes a substrate having a first conductivity type; a well region having a second conductivity type in the substrate; an impurity implantation region having the first conductivity type in the well region; an element separation pattern in the substrate; a first fin pattern defined by the element separation pattern in the impurity implantation region; a second fin pattern defined by the element separation pattern in the well region; and a third fin pattern defined by the element separation pattern in the substrate, wherein the first fin pattern is a single fin, and an entirety of a lower boundary of the impurity implantation region is in contact with the well region.

公开(公告)号：US20240421189A1

公开(公告)日：2024-12-19

申请号：US18596179

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Chang Woo Noh ,  Yu Jin Jeon

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a substrate including first and second regions, a first bridge pattern extending in a first direction on the first region, a first gate structure extending in a second direction intersecting the first direction, first epitaxial patterns connected to the first bridge pattern on side surfaces of the first gate structure, first inner spacers interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial patterns, a second bridge pattern extending in the first direction on the second region, a second gate structure extending in the second direction, second epitaxial patterns connected to the second bridge pattern on side surfaces of the second gate structure, and second inner spacers interposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial patterns.

公开(公告)号：US11843000B2

公开(公告)日：2023-12-12

申请号：US17336785

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Keun Hwi Cho

IPC: H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02603 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.