公开(公告)号：US11978770B2

公开(公告)日：2024-05-07

申请号：US17388225

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Dong Ko ,  Woo Cheol Shin ,  Soo Jin Jeong

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, first and second nanosheets stacked on the active pattern to be spaced apart from each other in a vertical direction, a gate electrode that extends in a second direction the active pattern, the gate electrode surrounding each of the first and second nanosheets, a source/drain region on at least one side of the gate electrode, and inner spacers between the gate electrode and the source/drain region, the inner spacers including a first inner spacer between the active pattern and the first nanosheet, and a second inner spacer between the first nanosheet and the second nanosheet, the second inner spacer having a first portion adjacent to the first nanosheet, and a second portion adjacent to the second nanosheet, the first portion being wider than the second portion.

公开(公告)号：US11139382B2

公开(公告)日：2021-10-05

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L27/12

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US20240363625A1

公开(公告)日：2024-10-31

申请号：US18422471

申请日：2024-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beom Jin Park ,  Myung Gil Kang ,  Dong Won Kim ,  Young Gwon Kim ,  Soo Jin Jeong

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor includes a substrate having a first conductivity type; a well region having a second conductivity type in the substrate; an impurity implantation region having the first conductivity type in the well region; an element separation pattern in the substrate; a first fin pattern defined by the element separation pattern in the impurity implantation region; a second fin pattern defined by the element separation pattern in the well region; and a third fin pattern defined by the element separation pattern in the substrate, wherein the first fin pattern is a single fin, and an entirety of a lower boundary of the impurity implantation region is in contact with the well region.

公开(公告)号：US12107135B2

公开(公告)日：2024-10-01

申请号：US17467660

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US11967614B2

公开(公告)日：2024-04-23

申请号：US17715273

申请日：2022-04-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/08 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/0847 ,  H01L29/045 ,  H01L29/78696

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.

公开(公告)号：US11322589B2

公开(公告)日：2022-05-03

申请号：US16752418

申请日：2020-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/04 ,  H01L29/786

Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.