公开(公告)号：US20240074192A1

公开(公告)日：2024-02-29

申请号：US18202019

申请日：2023-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yoon Kim ,  Byoung Jae Park ,  Jae-Hwang Sim ,  Jongseon Ahn ,  Young-Ho Lee

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06524

Abstract: A three-dimensional semiconductor device includes: a source structure including a cell region and an extension region; a gate stacking structure disposed on the source structure, the gate stacking structure including insulating patterns and conductive patterns, which are alternately stacked on each other; an insulating structure disposed on the gate stacking structure, the insulating structure including a plurality of insulating layers; a memory channel structure penetrating the gate stacking structure and electrically connected to the cell region; a separation structure penetrating the gate stacking structure and extending from the cell region to the extension region; and a penetration plug penetrating the gate stacking structure and the extension region, wherein the penetration plug includes: a first plug portion penetrating the gate stacking structure; and a second plug portion on the first plug portion, wherein the separation structure includes: a first separation portion penetrating the gate stacking structure; and a second separation portion on the first separation portion, and wherein a top surface of the first plug portion and a top surface of the first separation portion are at a substantially same level.

公开(公告)号：US10128120B2

公开(公告)日：2018-11-13

申请号：US15242190

申请日：2016-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangsu Kim ,  Byoung Jae Park ,  Yongsun Ko ,  Kyunghyun Kim ,  ChangSup Mun ,  Kijong Park

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: The inventive concepts provide a method of completely removing a damage region of a surface of an etch target layer after plasma-etching the etch target layer. The method includes performing a first post-etch plasma treatment process using a first post-treatment gas on the plasma-etched etch target layer. A polarity of ions of the first post-treatment gas may be the same as a polarity of bias power applied to a stage in a plasma apparatus.