公开(公告)号：US20250089314A1

公开(公告)日：2025-03-13

申请号：US18588089

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon HWANG ,  Hyojin KIM ,  Byungho MOON ,  Myungil KANG ,  Doyoung CHOI

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, including a first active region on a substrate, including a lower channel pattern and lower source/drain patterns connected to the lower channel pattern, the lower channel pattern including a plurality of lower semiconductor patterns stacked and spaced apart from each other in a first direction that is perpendicular to an upper surface of the substrate, and the lower semiconductor patterns including a lowermost first semiconductor pattern, a second active region stacked on the first active region, including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a lower gate electrode on the lower channel pattern, and a lower insulating pattern under the first semiconductor pattern, the first semiconductor pattern spaced apart from the lower insulating pattern in the first direction. The lower gate electrode includes a first portion adjacent to a first sidewall of the lower insulating pattern and extending in the first direction from an upper surface to a bottom surface of the lower gate electrode, a second portion adjacent to a second sidewall of the lower insulating pattern and extending in the first direction from the upper surface to the bottom surface of the lower gate electrode, the second sidewall facing the first sidewall in a second direction which is perpendicular to the first direction, and a third portion in contact with a bottom surface of the lower insulating pattern and extending from the first portion to the second portion in the second direction.

公开(公告)号：US20250107180A1

公开(公告)日：2025-03-27

申请号：US18755008

申请日：2024-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee CHO ,  Byungho MOON ,  Donghoon HWANG

IPC: H01L29/06 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device including a base substrate layer, a sheet separation wall extending on the base substrate layer in a first horizontal direction, a pair of nanosheet stacked structures including the sheet separation wall therebetween and apart from each other in a second horizontal direction, the second horizontal direction different from the first horizontal direction, the pair of nanosheet stacked structures each including a plurality of nanosheets, a plurality of cladding patterns between a first end of each of the plurality of nanosheets included in each of the pair of nanosheet stacked structures and the sheet separation wall, and a pair of gate electrodes extending on the pair of nanosheet stacked structures in the second horizontal direction.

公开(公告)号：US20240274686A1

公开(公告)日：2024-08-15

申请号：US18437473

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho MOON ,  Inchan HWANG ,  Doyoung CHOI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device, including a lower active region, a lower gate pattern surrounding the lower active region, a lower dielectric layer between the lower active region and the lower gate pattern, an intermediate insulating layer on the lower active region, an upper active region on the intermediate insulating layer, an upper gate pattern surrounding the upper active region and covering the lower gate pattern, and an upper dielectric layer between the upper active region and the upper gate pattern, wherein an upper surface of the lower gate pattern is located lower in a vertical direction than an upper surface of the intermediate insulating layer, and the lower gate pattern surrounds at least a portion of a side surface of the intermediate insulating layer.