公开(公告)号：US20250080829A1

公开(公告)日：2025-03-06

申请号：US18819074

申请日：2024-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwoong HAM ,  Nahye KIM ,  Hyerim KIM ,  Jeesu PARK ,  Wonkyu SUNG ,  Daekwang JUNG ,  Yunsu CHO ,  Doyoung CHOI ,  Inje HWANG ,  Jihea PARK

IPC: H04N23/62 ,  H04N23/667

Abstract: An electronic device according to an embodiment of the disclosure may include: a camera; at least one processor comprising processing circuitry; at least one display; a sensor having a sensing region on a side surface of the electronic device; and a memory. The memory may store instructions, and at least one processor, individually and/or collectively, is configured to: execute a camera application for controlling the camera; based on the camera application being executed, sense a vertical swipe input through the sensor; control a first function of the camera, based on the vertical swipe input; sense a horizontal swipe input through the sensor; and control a second function of the camera, based on the horizontal swipe input.

公开(公告)号：US20250053240A1

公开(公告)日：2025-02-13

申请号：US18752460

申请日：2024-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunwoong HAM ,  Nahye KIM ,  Hyerim KIM ,  Jeesu PARK ,  Wonkyu SUNG ,  Daekwang JUNG ,  Yunsu CHO ,  Doyoung CHOI ,  Inje HWANG ,  Jihea PARK

IPC: G06F3/01 ,  G06F3/041 ,  G08B6/00

Abstract: An example electronic device includes a housing, a display, communication circuitry, a first actuator configured to provide vibration feedback in response to receiving an incoming call event through the communication circuitry, a sensor configured to receive a user touch input with respect to a side surface of the housing, a second actuator configured to provide vibration feedback in response to receiving the user touch input, and a processor. The processor is configured to control the first actuator to provide first vibration feedback in response to the incoming call event; receive a designated user touch input with respect to the side surface of the housing while providing the first vibration feedback; and, in response to receiving the designated user touch input, control the first actuator to cease providing the first vibration feedback and control the second actuator to provide second vibration feedback.

公开(公告)号：US20250089314A1

公开(公告)日：2025-03-13

申请号：US18588089

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghoon HWANG ,  Hyojin KIM ,  Byungho MOON ,  Myungil KANG ,  Doyoung CHOI

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, including a first active region on a substrate, including a lower channel pattern and lower source/drain patterns connected to the lower channel pattern, the lower channel pattern including a plurality of lower semiconductor patterns stacked and spaced apart from each other in a first direction that is perpendicular to an upper surface of the substrate, and the lower semiconductor patterns including a lowermost first semiconductor pattern, a second active region stacked on the first active region, including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a lower gate electrode on the lower channel pattern, and a lower insulating pattern under the first semiconductor pattern, the first semiconductor pattern spaced apart from the lower insulating pattern in the first direction. The lower gate electrode includes a first portion adjacent to a first sidewall of the lower insulating pattern and extending in the first direction from an upper surface to a bottom surface of the lower gate electrode, a second portion adjacent to a second sidewall of the lower insulating pattern and extending in the first direction from the upper surface to the bottom surface of the lower gate electrode, the second sidewall facing the first sidewall in a second direction which is perpendicular to the first direction, and a third portion in contact with a bottom surface of the lower insulating pattern and extending from the first portion to the second portion in the second direction.

公开(公告)号：US20230052477A1

公开(公告)日：2023-02-16

申请号：US17719723

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon HA ,  Mingyu KIM ,  Doyoung CHOI

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device comprises an active pattern on a substrate, a pair of first source/drain patterns on the active pattern, a pair of second source/drain patterns on top surfaces of the first source/drain patterns, a gate electrode extending across the active pattern and having sidewalls that face the first and second source/drain patterns, a first channel structure extending across the gate electrode and connecting the first source/drain patterns, and a second channel structure extending across the gate electrode and connecting the second source/drain patterns. The gate electrode includes a first lower part between a bottom surface of the first channel structure and a top surface of the active pattern, and a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure. The first lower part has a thickness greater than that of the first upper part.

公开(公告)号：US20220399463A1

公开(公告)日：2022-12-15

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Doyoung CHOI ,  Daewon HA ,  Mingyu KIM

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.

公开(公告)号：US20240274686A1

公开(公告)日：2024-08-15

申请号：US18437473

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungho MOON ,  Inchan HWANG ,  Doyoung CHOI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A stacked integrated circuit device, including a lower active region, a lower gate pattern surrounding the lower active region, a lower dielectric layer between the lower active region and the lower gate pattern, an intermediate insulating layer on the lower active region, an upper active region on the intermediate insulating layer, an upper gate pattern surrounding the upper active region and covering the lower gate pattern, and an upper dielectric layer between the upper active region and the upper gate pattern, wherein an upper surface of the lower gate pattern is located lower in a vertical direction than an upper surface of the intermediate insulating layer, and the lower gate pattern surrounds at least a portion of a side surface of the intermediate insulating layer.

公开(公告)号：US20240014284A1

公开(公告)日：2024-01-11

申请号：US18195657

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Myungil KANG ,  Hyojin KIM ,  Doyoung CHOI

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786 ,  H01L29/775 ,  H01L23/528 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L27/092 ,  H01L29/78696 ,  H01L29/775 ,  H01L23/5283 ,  H01L29/41775 ,  H01L29/0673

Abstract: A semiconductor device includes an active region on a substrate; channel layers on the active region spaced apart from each other and including lower and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate intersecting the active region and including a lower gate electrode surrounding the lower channel layers and an upper gate electrode surrounding the upper channel layers; an insulating pattern between the upper and lower gate electrodes on a side of the intermediate insulating layer; source/drain regions on at least one side of the gate, and including lower source/drain regions connected to the lower channel layers and upper source/drain regions connected to the upper channel layers; and a contact plug including a horizontal extension portion connected to the lower source/drain regions, and a vertical extension portion connected to the horizontal extension portion.

公开(公告)号：US20230343782A1

公开(公告)日：2023-10-26

申请号：US18063937

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Minchan GWAK ,  Doyoung CHOI

IPC: H01L27/088 ,  H01L23/522 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L21/28 ,  H01L21/78 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L23/5226 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/28123 ,  H01L21/7806 ,  H01L21/823475 ,  H01L21/823481

Abstract: An integrated circuit device includes a channel area extending in a first horizontal direction, a gate cut structure having a tapered shape in which a horizontal width thereof decreases while extending from a lower side to an upper side in a vertical direction, and a pair of gate electrodes respectively having ends facing each other with the gate cut structure therebetween. The pair of gate electrodes may extend in a second horizontal direction intersecting with the first horizontal direction.

公开(公告)号：US20250126861A1

公开(公告)日：2025-04-17

申请号：US18745312

申请日：2024-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok PARK ,  Donghoon HWANG ,  Myungil KANG ,  Wookhwan SONG ,  Doyoung CHOI

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes: a substrate; an active region extending in a first direction on the substrate; a gate structure extending in a second direction on the active region and intersecting the active region; a source/drain region on the active region on a side of the gate structure; a separation pattern extending in the first direction and separating the gate structure; and a contact structure on the separation pattern and crossing the separation pattern, the contact structure being electrically connected to the source/drain region, wherein the contact structure includes a first portion and a second portion, the first portion contacts the separation pattern, the second portion contacts the source/drain region, a lower surface of the second portion is at a level lower than a lower surface of the first portion, and a lowermost end of the contact structure is spaced apart from the separation pattern.

公开(公告)号：US20240047456A1

公开(公告)日：2024-02-08

申请号：US17984042

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ming HE ,  Mehdi SAREMI ,  Rebecca PARK ,  Muhammed AHOSAN UL KARIM ,  Harsono SIMKA ,  Sungil PARK ,  Myungil KANG ,  Kyungho KIM ,  Doyoung CHOI ,  JaeHyun PARK

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/41725 ,  H01L29/0607 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/785

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.