公开(公告)号：US20240196617A1

公开(公告)日：2024-06-13

申请号：US18511396

申请日：2023-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin Lee ,  Jihwan Yu ,  Byungman Ahn ,  Bonghyun Choi

IPC: H10B43/27 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a substrate comprising a chip region and a scribe lane region including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region.