公开(公告)号：US20160216319A1

公开(公告)日：2016-07-28

申请号：US14957987

申请日：2015-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon NA ,  ChaeHoon KIM ,  HyunJin KIM ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/31716 ,  G01R31/2884 ,  G01R31/3177

Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

Abstract translation: 包括第一焊盘和第二焊盘的集成电路，分别连接到第一焊盘的第一接收器电路和第一驱动器电路，分别连接到第二焊盘的第二接收器电路和第二驱动器电路，以及第一回路电路， 电连接到第一接收器电路的输入端子，电连接到第一驱动器电路的第一输出端子，电连接到第二驱动器电路的第二输出端子和电连接到第二接收器电路的第二输入端子。 在正常模式下，第一回路电路将第一输入端子与第二输出端子电连接，并将第二输入端子电连接到第一输出端子。 在测试模式下，第一回路电路将第一输入端子与第一输出端子电连接。

公开(公告)号：US20180096718A1

公开(公告)日：2018-04-05

申请号：US15608219

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChaeHoon KIM ,  Kyoman Kang ,  Tae-Hong Kwon ,  Taeyun Lee ,  Jin-Young Chun

IPC: G11C11/4091 ,  G11C7/12

CPC classification number: G11C11/4091 ,  G11C5/145 ,  G11C7/06 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.