公开(公告)号：US20180122496A1

公开(公告)日：2018-05-03

申请号：US15632962

申请日：2017-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-MIN KANG ,  DONGKU KANG ,  KWANG WON KIM ,  HyunJin KIM

IPC: G11C29/00 ,  G06F11/10 ,  G11C16/16 ,  G11C16/12 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C29/789 ,  G06F11/1068 ,  G06F11/1072 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/1009 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/344 ,  G11C2211/5642

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.

公开(公告)号：US20160216319A1

公开(公告)日：2016-07-28

申请号：US14957987

申请日：2015-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daehoon NA ,  ChaeHoon KIM ,  HyunJin KIM ,  Jangwoo LEE ,  Jeongdon IHM

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/31716 ,  G01R31/2884 ,  G01R31/3177

Abstract: An integrated circuit including first pads and second pads, a first receiver circuit and a first driver circuit respectively connected to the first pad, a second receiver circuit and a second driver circuit respectively connected to the second pad, and a first loopback circuit having a first input terminal electrically connected to the first receiver circuit, a first output terminal electrically connected to the first driver circuit, a second output terminal electrically connected to the second driver circuit, and a second input terminal electrically connected to the second receiver circuit may be provided. At a normal mode, the first loopback circuit electrically connects the first input terminal to the second output terminal and electrically connects the second input terminal to the first output terminal. At a test mode, the first loopback circuit electrically connects the first input terminal to the first output terminal.

Abstract translation: 包括第一焊盘和第二焊盘的集成电路，分别连接到第一焊盘的第一接收器电路和第一驱动器电路，分别连接到第二焊盘的第二接收器电路和第二驱动器电路，以及第一回路电路， 电连接到第一接收器电路的输入端子，电连接到第一驱动器电路的第一输出端子，电连接到第二驱动器电路的第二输出端子和电连接到第二接收器电路的第二输入端子。 在正常模式下，第一回路电路将第一输入端子与第二输出端子电连接，并将第二输入端子电连接到第一输出端子。 在测试模式下，第一回路电路将第一输入端子与第一输出端子电连接。

公开(公告)号：US20210057037A1

公开(公告)日：2021-02-25

申请号：US17039798

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG-MIN KANG ,  DONGKU KANG ,  KWANG WON KIM ,  HyunJin KIM

IPC: G11C29/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C5/02 ,  G06F11/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array including first to fourth planes, a page buffer circuit that includes first to fourth page buffer units connected with the first to fourth planes, respectively, an input/output circuit that includes a first input/output unit connected with the first to fourth page buffer units and a second input/output unit connected with the second and fourth page buffer units, and control logic that controls the input/output circuit to output first data from one of the first to fourth page buffer units through the first input/output unit in a first read mode and output second data from one of the first and third page buffer units through the first input/output unit and third data from one of the second and fourth page buffer units through the second input/output unit in a second read mode.