公开(公告)号：US09503064B2

公开(公告)日：2016-11-22

申请号：US14792985

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeonghan Cha ,  Han-Kyul Lim ,  SungJun Kim ,  Chaeryung Kim ,  DongUk Park ,  Younwoong Chung ,  JungMyung Choi

IPC: H03L7/00 ,  H03K3/86 ,  G06F1/10 ,  H03K5/13 ,  H03K5/135 ,  H03K5/14

CPC classification number: H03K3/86 ,  G06F1/10 ,  H03K5/131 ,  H03K5/135 ,  H03K5/14

Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Abstract translation: 偏斜校准电路可以包括接收第一数据和第一代码的数据延迟单元，并且通过根据第一代码延迟第一数据来将延迟的第一数据作为第二数据输出; 时钟延迟单元，接收第一时钟信号和第二代码，并且通过根据第二代码延迟第一时钟信号，将延迟的第一时钟信号作为第二时钟信号输出; 多路复用器响应于选择信号，接收时钟信号并输出​​时钟信号或时钟信号的反相时钟信号作为第一时钟信号; 以及控制逻辑单元，其接收第二数据和第二时钟信号，并且响应于第二数据和第二时钟信号来控制第一代码，第二代码和选择信号。

公开(公告)号：US11687143B2

公开(公告)日：2023-06-27

申请号：US17483932

申请日：2021-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaeryung Kim ,  Kiwoon Kim ,  Jiun Jeong ,  Hoyoung Kim ,  Dongjun Park ,  Dongyoung Song ,  Kyuik Cho ,  Gyeonghan Cha

IPC: G06F1/3234 ,  G06F13/40 ,  G06F1/26

CPC classification number: G06F1/3253 ,  G06F13/4068 ,  G06F13/4086 ,  G06F1/266

Abstract: An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor.