公开(公告)号：US10284360B2

公开(公告)日：2019-05-07

申请号：US15415336

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho Choi ,  Younwoong Chung

IPC: H03K5/133 ,  H04L7/00 ,  H03L7/08 ,  H03L7/099 ,  H03K5/00

Abstract: An electronic circuit receives transmission signals from three or more communication lines. The electronic circuit includes a clock-data recovery circuit and a control value generation circuit. The clock-data recovery circuit outputs a recovered clock based on a transition generated in reception signals. The clock-data recovery circuit outputs recovered signals based on the recovered clock and the reception signals. The recovered clock has a first edge in response to the transition generated in the reception signals. The recovered clock has a second edge in response to a reset signal generated based on a delay of the recovered clock. The delay of the recovered clock is adjusted based on a control value provided from the control value generation circuit. The control value is adjusted based on change of a communication condition.

公开(公告)号：US11606113B2

公开(公告)日：2023-03-14

申请号：US17384991

申请日：2021-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younwoong Chung ,  Yungeun Nam ,  Jongshin Shin

IPC: H04B1/40 ,  H04B17/19 ,  H03K19/00

Abstract: Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.

公开(公告)号：US09503064B2

公开(公告)日：2016-11-22

申请号：US14792985

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeonghan Cha ,  Han-Kyul Lim ,  SungJun Kim ,  Chaeryung Kim ,  DongUk Park ,  Younwoong Chung ,  JungMyung Choi

IPC: H03L7/00 ,  H03K3/86 ,  G06F1/10 ,  H03K5/13 ,  H03K5/135 ,  H03K5/14

CPC classification number: H03K3/86 ,  G06F1/10 ,  H03K5/131 ,  H03K5/135 ,  H03K5/14

Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Abstract translation: 偏斜校准电路可以包括接收第一数据和第一代码的数据延迟单元，并且通过根据第一代码延迟第一数据来将延迟的第一数据作为第二数据输出; 时钟延迟单元，接收第一时钟信号和第二代码，并且通过根据第二代码延迟第一时钟信号，将延迟的第一时钟信号作为第二时钟信号输出; 多路复用器响应于选择信号，接收时钟信号并输出​​时钟信号或时钟信号的反相时钟信号作为第一时钟信号; 以及控制逻辑单元，其接收第二数据和第二时钟信号，并且响应于第二数据和第二时钟信号来控制第一代码，第二代码和选择信号。