公开(公告)号：US20140369115A1

公开(公告)日：2014-12-18

申请号：US14155651

申请日：2014-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae KIM ,  Young-Tak KIM ,  Ho-Sung SON ,  Seok-Jun WON ,  Ji-Hye YI ,  Chul-Woong LEE

IPC: H01L29/78 ,  G11C11/40

CPC classification number: H01L29/7851 ,  H01L29/41783 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Abstract translation: 提供半导体装置及其制造方法以及包括半导体装置的电子装置。 半导体器件包括形成在衬底上并包括沟槽的层间绝缘层，形成在沟槽中的栅电极，形成在栅电极的侧壁上以形成L形的第一栅极间隔件，形成在第二栅极间隔 所述第一栅极间隔物具有L形并且具有低于氮化硅的介电常数的介电常数，以及形成在所述第二栅极间隔物上的第三间隔物。

公开(公告)号：US20170186869A1

公开(公告)日：2017-06-29

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.