公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20170186869A1

公开(公告)日：2017-06-29

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20170110581A1

公开(公告)日：2017-04-20

申请号：US15393852

申请日：2016-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/167

CPC classification number: H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US20150214051A1

公开(公告)日：2015-07-30

申请号：US14516603

申请日：2014-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

Abstract translation: 一种制造半导体器件的方法包括：部分去除负载在腔室中的衬底的有源鳍片的上部，以形成沟槽; 以及在所述沟槽中形成源极/漏极层，所述源极/漏极层包括提供硅源气体，锗源气体，蚀刻气体和载气，以进入所述腔室中，以使用所述顶部表面进行选择性外延生长（SEG） 活性鳍作为种子由沟槽暴露，使得硅 - 锗层生长; 以及通过将载气提供到所述室中来清洗所述室，以蚀刻所述硅 - 锗层。

公开(公告)号：US20140035051A1

公开(公告)日：2014-02-06

申请号：US14050469

申请日：2013-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dong-Suk SHIN ,  Jung-Deog LEE

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6656

Abstract: A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.

Abstract translation: 一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物， 源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物， 源极漏极区域。

公开(公告)号：US20210119036A1

公开(公告)日：2021-04-22

申请号：US17119507

申请日：2020-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Sung-Min KIM ,  Dong-Suk SHIN ,  Seung-Hun LEE ,  Dong-Won KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

公开(公告)号：US20190081168A1

公开(公告)日：2019-03-14

申请号：US16045305

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan YU ,  Sung-Min KIM ,  Dong-Suk SHIN ,  Seung-Hun LEE ,  Dong-Won KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/11

Abstract: A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.

公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20160247924A1

公开(公告)日：2016-08-25

申请号：US15146106

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

Abstract translation: 一种制造半导体器件的方法包括：部分去除负载在腔室中的衬底的有源鳍片的上部，以形成沟槽; 以及在所述沟槽中形成源极/漏极层，所述源极/漏极层包括提供硅源气体，锗源气体，蚀刻气体和载气，以进入所述腔室中，以使用所述顶部表面进行选择性外延生长（SEG） 活性鳍作为种子由沟槽暴露，使得硅 - 锗层生长; 以及通过将载气提供到所述室中来清洗所述室，以蚀刻所述硅 - 锗层。

公开(公告)号：US20150221654A1

公开(公告)日：2015-08-06

申请号：US14519516

申请日：2014-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

Abstract translation: 半导体器件包括：衬底，其包括多个第一有源区和多个第二有源区; 分别形成在第一有源区上方的多个第一栅极结构和分别形成在第二有源区上方的多个第二栅极结构; 以及分别对应于第一栅极结构的多个第一源极/漏极层和分别对应于第二栅极结构的多个第二源极/漏极层，其中每个第一源极/漏极层的宽度较小 比第二源极/漏极层的宽度宽。