公开(公告)号：US20170186869A1

公开(公告)日：2017-06-29

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk SHIN ,  Hyun-Chul KANG ,  Dong-Hyun ROH ,  Pan-Kwi PARK ,  Geo-Myung SHIN ,  Nae-In LEE ,  Chul-Woong LEE ,  Hoi-Sung CHUNG ,  Young-Tak KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US20150214051A1

公开(公告)日：2015-07-30

申请号：US14516603

申请日：2014-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

Abstract translation: 一种制造半导体器件的方法包括：部分去除负载在腔室中的衬底的有源鳍片的上部，以形成沟槽; 以及在所述沟槽中形成源极/漏极层，所述源极/漏极层包括提供硅源气体，锗源气体，蚀刻气体和载气，以进入所述腔室中，以使用所述顶部表面进行选择性外延生长（SEG） 活性鳍作为种子由沟槽暴露，使得硅 - 锗层生长; 以及通过将载气提供到所述室中来清洗所述室，以蚀刻所述硅 - 锗层。

公开(公告)号：US20160247924A1

公开(公告)日：2016-08-25

申请号：US15146106

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

Abstract translation: 一种制造半导体器件的方法包括：部分去除负载在腔室中的衬底的有源鳍片的上部，以形成沟槽; 以及在所述沟槽中形成源极/漏极层，所述源极/漏极层包括提供硅源气体，锗源气体，蚀刻气体和载气，以进入所述腔室中，以使用所述顶部表面进行选择性外延生长（SEG） 活性鳍作为种子由沟槽暴露，使得硅 - 锗层生长; 以及通过将载气提供到所述室中来清洗所述室，以蚀刻所述硅 - 锗层。

公开(公告)号：US20150221654A1

公开(公告)日：2015-08-06

申请号：US14519516

申请日：2014-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk KIM ,  Geo-Myung SHIN ,  Dong-Suk SHIN

IPC: H01L27/11 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L27/092 ,  H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

Abstract translation: 半导体器件包括：衬底，其包括多个第一有源区和多个第二有源区; 分别形成在第一有源区上方的多个第一栅极结构和分别形成在第二有源区上方的多个第二栅极结构; 以及分别对应于第一栅极结构的多个第一源极/漏极层和分别对应于第二栅极结构的多个第二源极/漏极层，其中每个第一源极/漏极层的宽度较小 比第二源极/漏极层的宽度宽。