公开(公告)号：US20160267949A1

公开(公告)日：2016-09-15

申请号：US15164442

申请日：2016-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HOON HAN ,  DONG-WAN KIM ,  JU-IK LEE

IPC: G11C5/06 ,  H01L23/535 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

公开(公告)号：US20230146012A1

公开(公告)日：2023-05-11

申请号：US17954394

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYEON-WOO JANG ,  DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  SOOHO SHIN ,  JIHOON CHANG

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10897

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.

公开(公告)号：US20210335743A1

公开(公告)日：2021-10-28

申请号：US17371405

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IK LEE ,  DONG-WAN KIM ,  SEOKHO SHIN ,  JUNG-HOON HAN ,  SANG-OH PARK

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L23/522 ,  H01L25/18 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

公开(公告)号：US20230041059A1

公开(公告)日：2023-02-09

申请号：US17857395

申请日：2022-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONG-WAN KIM ,  Keonhee PARK ,  DONG-SIK PARK ,  Joonsuk PARK ,  JIHOON CHANG ,  HYEON-WOO JANG

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

公开(公告)号：US20200013745A1

公开(公告)日：2020-01-09

申请号：US16455788

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： JU-IK LEE ,  DONG-WAN KIM ,  SEOK-HOSEAN SHIN ,  JUNG-HOON HAN ,  SANG-OH PARK

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor substrate and a connection terminal, including a base pillar, on the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, the insulation layer including an opening in the insulation layer through which the base pillar extends, wherein a side wall of the insulation layer defining the opening includes a horizontal step at a level that is lower than an uppermost portion of the base pillar.

公开(公告)号：US20150262625A1

公开(公告)日：2015-09-17

申请号：US14554113

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HOON HAN ,  DONG-WAN KIM ,  JU-IK LE

IPC: G11C5/06 ,  H01L23/532 ,  H01L27/105 ,  H01L23/528

CPC classification number: G11C5/063 ,  G11C7/18 ,  H01L21/764 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a bit line structure located on a semiconductor substrate, an outer bit line spacer located on a first side surface of the bit line structure, an inner bit line spacer including a first part located between the bit line structure and the outer bit line spacer and a second part located between the semiconductor substrate and the outer bit line spacer, and a block bit line spacer located between the outer bit line spacer and the second part of the inner bit line spacer. A first air-gap is defined by the outer bit line spacer, the inner bit line spacer, and the block bit line spacer.

Abstract translation: 半导体器件包括位于半导体衬底上的位线结构，位线在位线结构的第一侧表面上的外部位线间隔件，内部位线间隔件包括位于位线结构和外部位之间的第一部分 并且位于半导体衬底和外部位线间隔物之间​​的第二部分和位于外部位线间隔物和内部位线间隔物的第二部分之间的块位线间隔件。 第一气隙由外部位线间隔件，内部位线间隔件和块位线间隔件限定。